Technical data

1.3 Functional Description

This chapter gives a functional description of the integrated PHYs on ERTEC 200 based on the block

diagram shown in

Figure 1 . Figure 1 shows a single channel; both channels have identical structure.

The subsequent chapters will frequently refer to signals that are present on the MII interface between

on-chip PHY and on-chip MAC. In these cases the signal names that have been introduced in \1\Table

1.5.7 and 1.5.8 will be used. Note that these signals can be externally monitored when ERTEC 200

has been configured to MII diagnosis mode with the CONFIG(6:1) pins.

Figure 1: PHY Block Diagram

1.3.1 10BASE-T Operation

A 10BASE-T transceiver is implemented for a 10 Mbps CSMA/CD LAN over two pairs of twisted-pair

wires according to the specifications given in clause 14 of the IEEE 802.3 standard. During transmis-

sion, 4-bit nibble data comes from the MII interface at a rate of 2.5 MHz and is converted into a

10 Mbps serial data stream. The data stream is then Manchester-encoded and sent to the analog

transmitter which drives a signal to the twisted pair cable via external magnetics.

In order to comply with legacy 10BASE-T MAC/Controllers, the transmitted data is looped back to the

receive path, if the PHY is configured to work in half-duplex mode.

On the receiver side, the receive clock is recovered from the incoming signal. The received Manches-

ter-encoded analog signal from the cable is recovered to the NRZI data stream using the clock. Then

the 10 Mbps serial data stream is again converted to 4-bit data that are passed to the MAC across the

MII interface at a rate of 2.5 MHz.

Technical data subject to change Version 1.0.0