Technical data

P2VSSATX DGND DVDD DGND DVDD
VDD33ES GND33ES
P1VDDARXT
P1VSSAR
P1VSSATX P1VSSATX VDDAPL
VDDAC VSSAPLLC
P2VSSATX
P2VSSAR
P2VDDARXT
DGND DVDD DGND DVDD
Power
Decou
p
lin
g
with 0.1
µ
F
Decoupling with 10nF and 22nF as
close to
GN
VDD Core
VDD IO
(
3.3
ERTEC
Figure 6: Decoupling Capacitor Usage
1.6.2 10BASE-T and 100BASE-TX Mode Circuitry
The analog input and output signals are very noise sensitive and PCB layout of these signals should be
done very carefully. P(2:1)TxN, P(2:1)TxP, P(2:1)RxN and P(2:1)RxP must be routed with differential
100
Ω impedance and the trace length must be kept as short as possible. The EXTRES input must be
connected to analog GND with a 12.4 k
Ω resistor (1% tolerance). Figure 7 and Figure 8 show typical
circuit examples for 10BASE-T and /or 100BASE-TX operation modes.
50 Ω 50 Ω 10 Ω
50 Ω 50 Ω 10 Ω
12.4k
75 Ω
75 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
10 nF
10 nF
10 nF / 2 kV
3.3 V
AGND
AGND
AGND
Case GND
ERTEC 200
P(2:1)TxP
P(2:1)RxN
P(2:1)TxN
P(2:1)TxP
EXTRES
RJ45
1
2
4
5
3
6
7
8
Unmarked resistors: 1/16 W and 1% tolerance
Resistors marked with „
•“
:
1/8 W and 1% tolerance
•
•
•
•
See Table 46
Figure 7: 10BASE-T and 100BASE-TX Interface Circuit Example 1
Copyright © Siemens AG 2008. All rights reserved. Page 53 ERTEC 200 PHY
Technical data subject to change Version 1.0.0