Technical data

1.6 Board Design Recommendations

In this chapter some board design recommendations will be given with respect to

• supply voltage circuitry

• “line” interfaces for 10BASE-T, 100BASE-TX and 100BASE-FX

• unused “line” interfaces

1.6.1 Supply Voltage Circuitry

ERTEC 200 works with two operating voltages: VDD Core (1.5 V) and VDD IO (3.3 V). Additionally the

on-chip PLL for the device clock generation requires a supply voltage called PLL_AVDD of 1.5 V, that is

typically a filtered version of VDD Core.

The on-chip PHYs of ERTEC 200 require additional filtered operating voltages as shown in \1\ Table

1.5.8. The subsequent

Table 45 illustrates, how these supply voltage are related to the “normal” VDD

Core and VDD IO.

Pin Name Function Supply Voltage Generation

P(2:1)VDDARXTX

nalog port RX/TX power supply, 1.5 V Must be generated from VDD

Core (1.5 V) via a filter.

VDDAPLL

nalog central power supply, 1.5 V

VDDACB

nalog central power supply, 3.3 V Must be generated from VDD IO

(3.3 V) via a filter.

VDD33ESD

nalog test power supply, 3.3 V

DVDD(4:1) Digital power supply, 1.5 V No filter required; just capacitive

decoupling from VDD Core

P(2:1)VSSARX

nalog port GND Must be generated from GND

Core /IO via a filter or connected

to GND Core/IO at the far end

from ERTEC 200.

P(2:1)VSSATX(2:1)

nalog port GND

VSSAPLLCB

nalog central GND

VSS33ESD

nalog test GND

DGND(4:1) Digital GND No filter required; just capacitive

decoupling from GND Core

Table 45: Generation of PHY-specific Supply Voltages

Beside filtering, the PHY-specific supply voltages should be equipped with pairs of decoupling capaci-

tors: 10nF and 22 nF capacitors should be used for DVDD(3:2), VDDESD, VDDAPLL, VDDACB and

P(2:1)VDDARXTX; they should be placed as close as possible to the chip. Additonally pairs of 0.1 and

22µF capacitors should be applied to DVDD4 , DVDD1, VDD3ESD and P(2:1)VDDARXTX.

Figure 6 shows the proposed circuit.

Technical data subject to change Version 1.0.0