Technical data

During a hardware reset or when the PHYs are driven out of the power down state (by setting the

P1/2_PHY_ENB bits in the PHY_CONFIG register to 1

), a pre-defined configuration is set in the regis-

ters. This configuration is partly hardwired and affects the initial settings of PHY-internal registers.

Table 10 shows these settings; the initial configuration can be altered later by writing to the PHY-internal

registers.

Name Description Port 1 Port 2

P1/2_PHYADDRESS(4:0) PHY address 00000

00001

P1/2_PHYMODE(2:0) PHY mode depends on PHY_CONFIG register setting

P1/2_MIIMODE(1:0) Interface mode of PHY permanently set to MII mode

P1/2_SMIISOURCESYNC SMII source mode permanently set to normal mode

P1/2_FXMODE 100BASE-FX mode depends on PHY_CONFIG register setting

P1/2_AUTOMDIXEN Enable AutoMDIX state machine depends on PHY_CONFIG register setting

P1/2_NPMSGCODE(2:0) Test of next page function permanently set to 000

P1/2_PHYENABLE Enables the PHYs depends on PHY_CONFIG register setting

REG2OUIIN(15:0) Default value for SMII register 2 0033H

REG3OUIIN(15:0) Default value for SMII register 3 2001H

Table 10: Initial Parameter Settings for PHYs

1.5.1 Basic Control Register

15 14 13 12 11 10 9 8 No. Initial value

Reset Loopback Speed

selection

Auto-

Negotiatio

n Enable

Power

Down

Isolate Restart

Auto-

Negotiatio

Duplex

Mode

xxxxH

Note

7 6 5 4 3 2 1 0

Collision

Test

Reserved

Table 11: Basic Control Register Overview

Note: The initial value depends on the setting of the P(2:1)_PHY_MODE(2:0) bits in the PHY1/2 Con-

figuration Register in the System Control Register block.

Technical data subject to change Version 1.0.0