Technical data

ManualsBrandsSiemens ManualsSwitchERTEC200

Table 3 shows the assignment of GPIO pins to these status informations.

(6) Other Signals

There are a few other signals - mainly supply voltages - related to the PHYs summarized in

Table 8.

Pin Name

Note

I/O Function Alternate Function

Note

RES_PHY_N O Reset signal to PHYs LBU_D14

EXTRES I/O

External reference resistor (12.4 kΩ)

Note

DVDD(4:1) I Digital power supply, 1.5 V -

DGND(4:1) I Digital GND -

P(2:1)VSSATX(2:1) I

nalog port GND -

P(2:1)VDDARXTX I

nalog port RX/TX power supply, 1.5 V -

P(2:1)VSSARX I

nalog port GND -

VDDAPLL I

nalog central power supply, 1.5 V -

VDDACB I

nalog central power supply, 3.3 V -

VSSAPLLCB I

nalog central GND -

VDD33ESD I

nalog test power supply, 3.3 V -

VSS33ESD I

nalog test GND -

Table 8: Other PHY Related Signals

Note: The external resistor must have a maximum tolerance of 1%.

1.5 PHY Register Description

Via the SMI interface access is given to the internal registers listed in Table 9. Note that these regis-

ters are implemented for each PHY. During write or read accesses the registers are selected using

their register number as an address. The PHY internal registers are not memory mapped.

0 Basic control register

1 Basic status register

Basic

2 PHY identifier 1

3 PHY identifier 2

4 Auto negotiation advertisement register

5 Auto negotiation link partner ability register (base page)

Auto negotiation link partner ability register (next page)

6 Auto negotiation expansion register

7 Next page transmit register

Extended

8-15 Reserved -

16 Silicon revision register

17 Mode control/status register

18 Special mode register

19-26 Reserved

27 Special control/status indication register

28 Reserved

29 Interrupt source register

30 Interrupt mask register

31 PHY special control/status register

Vendor specific

Table 9: PHY internal Registers

Technical data subject to change Version 1.0.0