Technical data
PHY Pin Name
Note
I/O Function Alternate Function
Note
TXD_P2(3:0) O Transmit data port 2 bits LBU_D(9:6)
RXD_P23 O Receive data port 2 bit 3 LBU_A11/PIPESTA2
RXD_P22 O Receive data port 2 bit 2 LBU_A10/TRACESYNC
RXD_P21 O Receive data port 2 bit 1 LBU_A9/TRACEPKT0
RXD_P20 O Receive data port 2 bit 0 LBU_A8/TRACEPKT1
TX_EN_P2 O Transmit enable port 2 LBU_D10
CRS_P2 O Carrier sense port 2 LBU_A12
RX_ER_P2 O Receive error port 2 PIPESTA0
TX_ERR_P2 O Transmit error port 2 LBU_D11
RX_DV_P2 O Receive data valid port 2 LBU_A14
COL_P2 O Collision port 2 LBU_A15
RX_CLK_P2 O Receive clock port 2 LBU_BE1_N
PHY 2
TX_CLK_P2 O Transmit clock port 2 LBU_RD_N
TXD_P1(3:0) O Transmit data port 1 bits LBU_D(3:0)
RXD_P13 O Receive data port 1 bit 3 LBU_A3/TRACEPKT6
RXD_P12 O Receive data port 1 bit 2 LBU_A2/TRACEPKT7
RXD_P11 O Receive data port 1 bit 1 LBU_A1/ETMEXTIN1
RXD_P10 O Receive data port 1 bit 0 LBU_A0/ETMEXTOUTT
TX_EN_P1 O Transmit enable port 1 LBU_D4
CRS_P1 O Carrier sense port 1 LBU_A4/TRACEPKT5
RX_ER_P1 O Receive error port 1 LBU_A5/TRACEPKT4
TX_ERR_P1 O Transmit error port 1 LBU_D5
RX_DV_P1 O Receive data valid port 1 LBU_A6/TRACEPKT3
COL_P1 O Collision port 1 LBU_A7/TRACEPKT2
RX_CLK_P1 O Receive clock port 1 LBU_BE0_N
PHY1
TX_CLK_P1 O Transmit clock port 1 LBU_WR_N
Table 5: MII (Diagnosis) Interface Signals
Note: MII diagnosis interface pins are alternatively used as local bus interface or trace pins; in this table the I/O
type is listed for the MII diagnosis function
(2) SMI Interface
The serial management interface (SMI) between MAC and PHY gives access to the PHY’s internal
control registers. There is a common SMI interface for both PHYs; the two PHYs have hardwired
addresses, that are part of the protocol over the SMI interface. The SMI signals can as well be moni-
tored together with the MII signals in MII diagnosis mode.
Table 6 lists the signals that belong to the SMI (diagnosis) interface and the “normal” usage of the
same pins for LBU signals.
Pin Name
Note
I/O Function Alternate Function
Note
SMI_MDC O Serial management interface clock LBU_D12
SMI_MDIO O Serial management interface data input/output LBU_D13
Table 6: SMI (Diagnosis) Interface Signals
Copyright © Siemens AG 2008. All rights reserved. Page 23 ERTEC 200 PHY
Technical data subject to change Version 1.0.0










