Technical data

1.4 PHY Related Interfaces

Like any other peripheral on the ERTEC 200 the PHYs have internal registers that allow control over

their behaviour and that reflect their operation status; however in contrast to the other peripherals, the

PHY control registrs are not memory mapped and not directly accessible for the ARM CPU core or any

other AHB master within ERTEC 200. This is due to the standardized MII/SMI interface between the

PHYs and the MACs that are integrated in the IRT switch.

Figure 5 shows the different paths into the

PHYs.

Figure 5: PHY Related Interfaces

The control and communication paths into and out of the PHYs can be categorized in four respectively

five groups.

(1) MII Interface

The media independent interface (MII) is the data communication interface between MAC and PHY;

each PHY (respectively each MAC) has its own MII interface. The two MII interfaces on ERTEC 200

are on-chip interfaces however they can be externally monitored, if ERTEC 200 is configured to MII

diagnosis mode. LBU interface pins are used for this purpose.

Table 5 lists the signals that belong to the MII diagnosis interface and the “normal” usage of the same

pins for LBU signals.

Technical data subject to change Version 1.0.0