Technical data

(8) Interrupt handling

Each PHY can generate a collective interrupt that can be triggered by several PHY-internal events;

these two interrupts are routed with a wired-OR to the common IRQ9 input of the ERTEC 200 interrupt

controller.

Table 4 shows the events that can generate an interrupt from the PHYs:

Interrupt number Interrupt Event

INT8 not used

INT7 ENERGYON generated

INT6

uto-negotiation complete

INT5 Remote fault detected

INT4 Link down

INT3

uto-negotiation LP acknowledge

INT2 Parallel detection fault

INT1

uto-negotiation page received

Table 4: PHY Interrupt Events

Each of the interrupt events above is described in the protocol of the Interrupt Source Flag register in

the PHYs; it can as well be masked or unmasked individually in the Interrupt Mask register in the

PHYs (see

Table 42: Interrupt Mask Register Description).

(9) Isolate Mode

The PHY data path may be electrically isolated from the MII by setting the Isolate bit in the Basic Con-

trol register to 1

. In isolate mode, the internal MII interface of the respective PHY is made inactive.

However the PHYs still respond to management transactions. Isolation provides a means for multiple

PHYs to be connected to the same MII without contention occurring and it is not really required to use

on ERTEC 200. The PHYs are not in isolate mode on power-up.

(10) Link integrity Test

The PHYs perform a link integrity test as outlined in the IEEE 802.3 Link Monitor state diagram. The

link status is multiplexed with the 10Mbps link status to form the reportable Link Status bit in the Basic

Control register 1, and is driven to the P(2:1)-LINK-LED_N output.

The DSP block indicates a valid MLT-3 waveform present on the P(2:1)RxP and P(2:1)RxN inputs as

defined by the ANSI X3.263 TP-PMD standard, to the link monitor state-machine, using an internal

signal called DATA_VALID. When it is asserted the control logic moves into a link-ready state, and

waits for an enable from the auto-negotiation block. When received, the link-up state is entered, and

the transmit and receive logic blocks become active.Should auto-negotiation be disabled, the link

integrity logic moves immediately to the link-up state, when the DATA_VALID signal is asserted.

Note that to allow the link to stabilize, the link integrity logic will wait a minimum of 330 µsec from the

time DATA_VALID is asserted until the link-ready state is entered. Should the DATA_VALID input be

negated at any time, this logic will immediately negate the link signal and enter the link-down state.

When the 10/100 digital block is in 10BASE-T mode, the link status generated from the 10BASE-T

receiver logic.

Technical data subject to change Version 1.0.0