Technical data

In this mode, the complete preamble, SFD and EFD are re-generated by the PHY so that always

complete packets are transmitted, even if received packets lack part of the preamble. The Isolate

bit in the Basic Control register needs to be cleared to work in remote loopback mode.

(5) Power Down Modes

(a) Hardware power down

This state is entered after a hardware reset of ERTEC 200. The PHYs are switched off and their

power consumption is almost 0 W. This state is left by setting the P1/2_PHY_ENB bits in the

PHY_CONFIG register. All analog and digital blocks in the PHYs are initialized and the pre-

defined configuration in the PHY_CONFIG register is copied to the PHYs. Then, the PHY-internal

registers can be configured as well.

Setting the P1/2_PHY_ENB bits extends the internal reset signal in the PHYs to 5.2 ms in order

to stabilize the PLL and all analog and digital blocks. When the PHYs are ready to operate, this is

automatically indicated in the PHY_STATUS registers with the P1/2_PWRUPRST bits (set to 1

(b) Software power down

This state is entered by writing a 1

into the PowerDown bit of the Basic Control register of the

PHYs. The affected PHY will then go into a low power state, where the MDIO interface is still

active, but where no activity is possible on the MII interface. The power consumption of the PHYs

in low power state is around 15 mW per PHY.

The low power mode is left by writing a 0

into the PowerDown bit. The digital parts of the

circuitry are re-initialised, however the start-up configuration, that is stored in the PHY_CONFIG

Leaving the low power state generates an internal reset for the PHYs with a duration of 256 µs

for PLL stabilization.

The PHYs support an automatic power down mode, that is entered, if there is no activity on the

Ethernet line. To enable this mode, a 1

must be written into the EDPWRDOWN bit of the Mode

Control/Status register of the PHYs. No activity on the line will then automatically drive the PHY

into the low power mode with approximately 15 mW power consumption per PHY. If link pulses or

data packets are detected, the low power mode is automatically left with an internal reset of 256

µs and re-initialization of the circuitry. The first and possibly the second packet may be lost during

the energy detection process. No configuration data is copied from the PHY_CONFIG register to

the PHY at this point.

Automatic power down cannot be used as long as Auto-negotiation is enabled; therefore the

Auto-Negotiation Enable bit in the Basic Control register must be set to 0

for automatic power

down.

(6) Resetting the PHYs

(a)

Hardware reset

There are two methods to issue a hardware reset to the ERTEC 200 on-chip PHYs; the reset

source can be selected using the PHY_RES_SEL bit in the PHY_CONFIG register:

PHY_RES_SEL = 0 PowerOn reset via RESET_N input resets the PHYs

PHY_RES_SEL = 1 Internal RES_PHY_N signal from IRT switch resets the PHYs

Technical data subject to change Version 1.0.0