Technical data

(2) MDI/MDI-X crossover detection

The PHYs automatically detect and correct MDI/MDI-X crossover. This function can be disabled by

setting the AutoMDIX_en bit in the Mode Control/Status register to 0

. When it is disabled, crossover

must be corrected manually by setting the MDI mode bit in the same register accordingly.

(3) Polarity

This core automatically detects and corrects polarity reversal in wiring in 10BASE-T mode. The result

of polarity detection is indicated by the XPOL bit in the Special Control/Status Indications register.

Polarity is checked at end of packets in 10BASE-T. When a packet is corrupted by noise, the PHY

may mis-interprete information inside the packet as end of packet. In this case, the PHY may invert the

polarity and a maximum of three packets is be needed to detect the valid polarity again.

(4) Loopback mode

This ERTEC 200 PHYs support two loopback modes: internal loopback and remote loopback.

Figure 3 illustrates the differences between these two modes.

Figure 3: Internal and Remote Loopback Modes

(a) Internal loopback

This loopback mode is defined in the IEEE 802.3 specification; it is enabled by setting the Loop-

back bit in the Basic Control register to 1

. In this mode, the scrambled transmit data is looped

into the receive logic. The COL_P(2:1) signal will be inactive in this mode, unless the Collision

Test bit in the Basic control register is active.

When the internal loopback mode is active, the receive circuitry should be isolated from the net-

work medium. In this mode, the assertion of TX_EN_P(2:1) at the MII interface does not result in

the transmission of data on the network medium, and transmitters are powered down.

(b) Remote loopback

This mode is enabled by setting the FARLOOP BACK bit in the Mode Control/Status register to

. This mode can be used only when the PHYs are in 100BASE-TX or 100BASE-FX mode. In

this mode, packets that arrive at the receiver are looped back out to the transmitter. In 100BASE-

TX mode, the data path includes the ADC, DSP, PCS circuits; in 100BASE-FX mode, the data

path includes the PECL logic, clock recovery and PCS logic. As long as no data is received, IDLE

symbols are transmitted.

Technical data subject to change Version 1.0.0