Technical data

(7) Receive Data Valid / Receive Error

The receive data valid signal RX_DV_P(2:1) indicates that recovered and decoded nibbles are being

presented on the RXD_P1(3:0) respectively RXD_P2(3:0) outputs synchronous to RX_CLK_P(2:1).

RX_DV_P(2:1) becomes active after the /J/K/ delimiter has been recognized and RXD_P(2:1) is

aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test

indicates failure.

RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media

Independent Interface (MII).

During a frame, unexpected code-groups are considered as receive errors. Expected code groups are

the data set (0H through FH), and the /T/R/(ESD) symbol pair. When a receive error occurs, the

RX_ERR_P(2:1) signal is asserted and arbitrary data is driven onto the RXD lines. Should an error be

detected during the time that the /J/K/ delimiter is being decoded (bad SSD error), RX_ERR(2:1) is

asserted true and the value 1110

is driven onto the RXD_P(2:1) lines. Note that the valid vata signal

is not yet asserted when the bad SSD error occurs.

1.3.3 100BASE-FX Operation

This section describes main functions within the PHY in 100BASE-FX operation.

<1> NRZI to(from) NRZ converter

<2> Far End Fault Indication

<3> Timing recovery from received data

<4> Support MII,RMII, SMII and Symbol interface

The 100BASE-FX shares logic with 100BASE-TX; the differences between 100BASE-FX mode and

100BASE-TX mode are following,

<1> Transmit output/receive input is not scrambled or MLT3 encoded.

<2> All analog circuits except for the PLL are powered-down.

<3> Auto-Negotiation is disabled.

<4> The transmit data is output to a FX transmitter.

<5> The receive data is input to the FX ECL level detector instead of the equalizer.

<6> The FX interface has a signal detect input.

(1) Signal Detect

The signal detect signals P(2:1)SDxP/N are input signals to the PHY from the PMD FX transceiver.

Assertion of P(2:1)SDxP/N indicates a valid FX signal on the fiber. When SD is deactivated, the LINK

goes down and no data is sent to the controller.

(2) Far End Fault indication

Far End fault indication (FEFI) is a mechanism used to communicate physical status across a fiber

link. Each PHY monitors the status of its receive link using the Signal Detect input. If the PHY detects

a problem with its receive link, it communicates that to its link partner using the FEFI mechanism.

Technical data subject to change Version 1.0.0