Technical data

Copyright © Siemens AG 2013. All rights reserved. 41 EB 200P Manual
Technical data subject to change Version 1.0.1
Test and debug circuits configuration pin header pin out is described in the following table.
Function Signal Pin
Pin Signal
Sync(0) BNC tip pin 1 2 ERTEC GPIO(9)
Sync(1) BNC tip pin 3 4 ERTEC GPIO(0)
Trace Trace CS bus switch OE 5 6 GND
EEPROM EEPROM CS bus switch OE 7 8 GND
User GPIOs
User GPIOs CS bus switch OE
9
10
GND
UART UART CS bus switch OE 11 12 GND
TEMP TEMP CS bus switch OE 13 14 GND
F_XHIF(0) FPGA_CONFIG(0) 15 16 GND
F_XHIF(1) FPGA_CONFIG(1) 17 18 3.3V
F_XHIF(2) FPGA_CONFIG(2) 19 20 3.3V
F_XHIF(3) FPGA_CONFIG(3) 21 22 GND
None NC 23 24 NC
None NC 25 26 NC
None NC 27 28 NC
None NC 29 30 NC
Table 37 EB 200P board settings header pinout