Technical data

Technical data subject to change Version 1.0.1

2.5 Clock System of the EB 200P

2.5.1 Clock Source of PCI Express Interface

The PCI Express bus supplies the on-board FPGA of the EB 200P with its clock. From this signal, system clock for

FPGA of 125MHz is synthesized. If EB200P is working in standalone mode there is no clock source for FGPA.

2.5.2 Clock Source of EB 200P via a Quartz Crystal

By default, a 25 MHz quartz crystal supplies the EB 200P via the ERTEC. Quartz tolerance is 15ppm

The sum of the deviation from aging, temperature, voltage, vibration and shock for ERTEC 200P clocks should not

exceed 100ppm.