Technical data

Technical data subject to change Version 1.0.1

 3x I2C

2.1.5 PNIP

The PNIP provides the required function for PROFINET IO. It contains the following functions:

 Configuration register for PNIP

 64 Kbytes of K-RAM for RT and IRT communication

2.1.6 External Memory Controller (EMC)

EMC comprises of 2 different controllers, one supporting the SDRAM Memory devices (including Mobile SDRAM), the

other supporting asynchronous SRAM timing in different flavors, including Burst Flash ROM memory devices.

SDRAM-Controller features:

 16/32 Bit databus width

 PC133 SDRAM-compatible (125 MHz synchron is used in ERTEC 200P)

 1 Bank with max. 256 MByte SDRAM (32 Bit databus)

 SDRAM support for following parts:

o CAS-Latency: 2 or 3 clocks

o Bank-address bits (1/2/4 internal banks), realized via the lowest two bits of the address bus MA(1:0)

o 8/9/10/11 bits column-address MA(13), MA(11:2)

o max. 14 bits row-address MA(15:2)

Asynchronous Controller features:

 Can be set to 8/16/32-bit data bus width (for each chip select programmable) chip selects

 The timing for each chip select can be set individually

 The response to ready signal can be set individually for each chip select

 The default setting is slow timing for booting purposes

 A maximum of 64 MB address area for each chip select

 Acknowledgement delay monitoring for external components can be set by software

The boot medium is always expected on chip select signal XCS_PER0. EB 200P board is equipped with Burst Mode

FLASH connected to this CS signal. If extension board is used, one can reconnect chip select signals from the default

state to extension board by changing of resistors. The following blocks of the EB 200P can be selected with the chip-

select lines:

Chip Select I/O Function

XCS_PER0 Boot Flash / FLASH 2x 8Mbit x 16

XCS_PER1 reserved 8kbit x 32

XCS_PER2 extension board 16Mbit x 32

XCS_PER3 extension board 16Mbit x 32

Table 4 CS Areas of the EB 200P

2.1.7 Debug and Trace Interface

The ETM macro cell of the ARM926EJ-S can be used as a debug and trace interface in the ERTEC 200P. With this

interface, the user software running on the ARM926EJ-S and the user data can be analyzed and traced. The ETM

module is a standard module recommended by ARM on which various available debuggers can be run. If the trace

interface is used, the XHIF interface is not available (configuration setting "Trace On“, see Section 2.1.2). If the trace

interface is used, the required parameter assignment of the ETM macro cell must be performed with the debugger, so

that the required pins are switched to trace functionality.

For debug and trace functionality 38pin MICTOR connector is assembled on EB 200P. JTAG pins on MICTOR are

directly connected to JTAG interface on ERTEC 200P. Signals for tracing can be connected or disconnected to/from

ERTEC 200P GPIOs by bidirectional bus switch

The ETM macro cell is described in documents /9/ and /10/.