Technical data

Technical data subject to change Version 1.0.1

2 Hardware Structure of the EB 200P

2.1 ERTEC 200P

2.1.1 Function Overview

Refer to documents /1/ and /2/ for a detailed function description of the ERTEC 200P.

In this manual, only the main components are described briefly and represented in a block diagram.

The following four AHB masters are integrated in the ERTEC 200P:

 ARM926EJ-S with trace/debug port and high-performance interrupt controllers

 PNIP with 64 Kbytes of K-RAM for real-time Ethernet communication

 External host processor on the XHIF interface

 32-channel DMA controller

The following I/O blocks are available to the masters:

 External memory controller (EMC) with SDRAM and SRAM controller

 Two Ethernet interfaces with integrated MII PHYs

 Blocks connected to APB bus

 96-bit GPIO

 4x UART

 2x SPI

 3x I

 6 timers

 F-timer

 2x Watchdog

 Boot ROM

 System Control

 Peripherie Interface

 I-Filter

The multi-layer AHB bus system enables a largely independent operation of the masters. Internal arbitration logic

prevents access conflicts if multiple masters want to access the same I/O block. The function groups of the ERTEC

200P are shown in block diagram. For block diagram please refer to /1/