EB 200P . Evaluation Board ERTEC 200P Manual Copyright © Siemens AG 2013. All rights reserved. Technical data subject to change 1 EB 200P Manual Version 1.0.
Edition (09/2013) Disclaimer of Liability We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly. Necessary corrections are included in subsequent editions. Suggestions for improvement are welcomed. Copyright © Siemens AG 2012.
Preface Contents of this Manual Detailed description of the individual function groups of the EB 200P Connector pin assignment and jumper assignment Target Audience of this Manual This manual is intended for hardware developers who want to use the ERTEC 200P for new products. Experience working with processors and designing embedded systems and knowledge of Ethernet are required for this. The manual serves as a reference for software developers.
Guide To help you quickly find the information you need, this manual contains the following aids: o A complete table of contents as well as a list of all figures and tables in the manual are provided at the beginning of the manual. o A glossary containing definitions of important terms used in the manual is located following the appendices. o References to other documents are indicated by the document reference number enclosed in slashes (/No./).
Contents 1 Introduction .................................................................................................................................. 8 1.1 1.2 1.3 1.4 2 Procedure when using ERTEC 200P to develop your own PROFINET IO Device .................................. 8 Structure of the EB 200P .............................................................................................................................. 9 Features of the EB 200P ................................................
.12 Configuration pins for ERTEC 200P ............................................................................................................ 38 6.13 Configuration pins for onboard circuits ........................................................................................................ 39 7 8 Settings on the EB 200P............................................................................................................. 42 Structure of the EB 200P..........................................
List of Figures Figure 1: EB 200P with connected debugger........................................................................................................................ 9 Figure 2: Block diagram of EB 200P.................................................................................................................................... 10 Figure 3 Status LEDs on the card bracket .........................................................................................................................
1 Introduction This manual describes the procedure for using the ERTEC 200P for HW development of a PROFINET IO device and the properties of the EB 200P evaluation board. The intended use of the EB 200P evaluation board is as follows: It serves as a template for development of your own PROFINET IO device hardware. It supports development and testing of your own PROFINET IO device application software. It enables testing of your hardware on a supplementary board together with the EB 200P, where applicable.
1.2 Structure of the EB 200P The EB 200P is implemented in the form of a half-size PCI Express card. The PCI Express interface is used only for PC mode. In standard configuration the EB 200P is operated as a stand-alone module. The EB 200P is supplied by means of an external plug-in power supply (part of the development kit).For software debugging a JTAG interface is available, for more information about JTAG interface is in Chapter 5. Figure 1: EB 200P with connected debugger 1.
1.4 Block Diagram of the EB 200P Figure 2: Block diagram of EB 200P Copyright © Siemens AG 2013. All rights reserved. Technical data subject to change 10 EB 200P Manual Version 1.0.
2 Hardware Structure of the EB 200P 2.1 ERTEC 200P 2.1.1 Function Overview Refer to documents /1/ and /2/ for a detailed function description of the ERTEC 200P. In this manual, only the main components are described briefly and represented in a block diagram.
2.1.2 Operating Modes of the EB 200P Various configurations on the EB 200P can be set by means of jumpers X40.9/10 and X41.1/2. These jumpers are described in Section 7. The following configuration settings are possible on the ERTEC 200P.
Following table shows configuration jumpers for test and debugging. Pin headers are labeled X42 and X43.
3x I2C 2.1.5 PNIP The PNIP provides the required function for PROFINET IO. It contains the following functions: Configuration register for PNIP 64 Kbytes of K-RAM for RT and IRT communication 2.1.6 External Memory Controller (EMC) EMC comprises of 2 different controllers, one supporting the SDRAM Memory devices (including Mobile SDRAM), the other supporting asynchronous SRAM timing in different flavors, including Burst Flash ROM memory devices.
2.1.8 General Purpose Interface (GPIO) The GPIO interface of the ERTEC 200P consists of 96 I/O that can be configured for different functionality. GPIO(150) pins have interrupt capability.
GPIO(24) - - - - - - GPIO(25) Error - - - - - GPIO(26) Maintenance - - - - - GPIO(27) Diagnostic - - - - - GPIO(28) ProfiEnergy - - - - - GPIO(29) Sync - - - - - GPIO(30) FO-1 - - - - - GPIO(31) FO-2 XCE - - - - Table 7 Test circuits interconnections on EB 200P Switch LEDs User GPIOs UART*3 Debug FPGA POFs Configuration by bus switch yes (shared) yes no no no Configuration by jumper no no no no no GPIO(0) SW0 LED0 user GPIO0 -
GPIO(27) - - - - - - - GPIO(28) - - - - - - - GPIO(29) - - - - - - - GPIO(30) - - - - - - - GPIO(31) - - - - - - - Table 8 Debug circuits interconnections on EB 200P Note: *1 Configured by jumper at one time can be connected only input or output *2 Assembly option, shared pins with BNC connector, if assembled BNC must not be used or connected *3 UART means connection via USB - Serial convertor *4 DBACK and DBGRQ can be configured by jumper only on TRACE connector, on
2.2 Memory on EB 200P The following memory types are available on the EB 200P evaluation board: 2.2.1 SDRAM The SDRAM interface consists of 2 Micron type MT48H32M16LFBF-75IT blocks. 128-Mbyte memory capacity 32-bit data width 133 MHz clock frequency 2.2.2 Burst Mode FLASH The Flash interface consists of 2 Spansion type S29WS128P0PBAW00 blocks. 32-Mbyte memory capacity 32-bit data width 66 MHz maximum frequency 2.2.
2.3 Test and debug peripherals For easier development some test and debug circuits are assembled on board. Test and debug circuit can be selectively connected to ERTEC 200P GPIOs. Configuration is done by jumpers and details about configuration are described in chapter 6.13. All test and debug circuits are connected to GPIOs which are using 3.3V logic. 2.3.1 Status LEDs Two groups of status LEDs are integrated on EB200P. The first group is near the bracket with small holes.
Function Color Position Connection Sync Green Bracket GPIO(29) Resistor P Green Bracket PSU 750 MT Yellow Bracket GPIO(26) 750 Error Red Bracket GPIO(25) 750 Power Green PCB PSU 750 750 Error Red PCB GPIO(25) 750 Maintenance Yellow PCB GPIO(26) 750 Diagnostic Yellow PCB GPIO(27) 750 PROFIenergy Green PCB GPIO(28) 750 Sync Green PCB GPIO(29) 750 FO-1 Yellow PCB GPIO(30) 750 FO-2 Yellow PCB GPIO(31) 750 Table 10 Status LEDs connection Status LED
2.3.4 User GPIOs with LEDs and switch 16 GPIOs are available for the user via 2x10 pin header. GND and 3.3V pins are available on this pin header too. These 16 pins can be connected or disconnected to/from ERTEC 200P GPIOs by bidirectional bus switch (SN74CB3Q3384). Pin out for pin header and jumper configuration for test and debug circuits are described in chapter 2.1.2. To each GPIO available on pin header a LED is connected via buffer (SN74ALVCH16244DGGR).
2.4 Reset System of the EB 200P The reset system of the EB 200P has 4 reset paths: Power On Reset: This reset is generated during power up on the EB 200P. The RESET_N signal affects the following function units. Resetting of ERTEC 200P logic Resetting of the PCI Express side Resetting of the Page Mode Flash Resetting of the Burst Mode Flash PCI Express Reset: If the EB 200P is operated with an active host, the connected host reset signal resets just the PCI Express interface. ERTEC 200P is not reset.
2.5 Clock System of the EB 200P 2.5.1 Clock Source of PCI Express Interface The PCI Express bus supplies the on-board FPGA of the EB 200P with its clock. From this signal, system clock for FPGA of 125MHz is synthesized. If EB200P is working in standalone mode there is no clock source for FGPA. 2.5.2 Clock Source of EB 200P via a Quartz Crystal By default, a 25 MHz quartz crystal supplies the EB 200P via the ERTEC.
2.6 2.6.1 Ethernet Interfaces of the EB 200P Ethernet ports (X1) Two 100Mbit/s full duplex ports are available in ERTEC 200P. PHYs are integrated in ERTEC 200P package. Only external magnetics with RJ45 connector are necessary for PROFINET functionality. In the following table pin out of both wired Ethernet ports is described.
3 3.1 Memory Allocation of EB 200P Memory Mapping The four AHB masters of the ERTEC 200P use the memory area differently. For the complete memory mapping, please refer to document /1/. EB 200P memory devices are mapped to certain part of the memory which can be then accessed by AHB masters (ARM926, DMA, etc.). Start and End Address 2000 0000 … 27FF FFFF 3000 0000 … 31FF FFFF 3400 0000 … 3400 FFFF 3800 0000 … 3BFF FFFF 3C00 0000 … 3FFF FFFF Seg .
4 Operating Modes of the EB 200P In standalone mode, 24V / 1.5A power must be supplied on connector X10. Power good (PGD) is indicated by LED H10 on PCB and PWR on slot bracket. If external power is applied and the EB 200P card is plugged in the host PC, power is taken from external power source. Note: When the EB200P is plugged in the host PC and host PC is switched off, EB200P is switched off even if it is powered from external power source. 4.
5 Debug/ Boundary scan Interface Several functions of the module can be performed with the JTAG interface of the EB 200P. Debugging of the EB 200P on connector X31 (see circuit 1) Boundary scan of all boundary scan-capable ICs on connector X31 (see circuit 1) The debugging or boundary scan selection is specified with the ERTEC 200P input TAP SEL. TAP_SEL = Low BS disable Debugging selected. TAP_SEL = High BS enable Boundary scan selected.
6 Connectors of the EB 200P The following connectors are available on the EB 200P for the interface connection to external components and systems.
6.1 PCI Express x1 Interface In the following table pin out of PCIe x1 connector is described. Connector name: X60 Connector type: 36-pin PCB direct connector Pin no. Side B Side A Name Description Name 1 +12V 12 V power PRSNT1# Hot-Plug presence detect 2 +12V 12 V power +12V 12 V power 3 RSVD Reserved +12V 12 V power 4 GND Ground GND Ground 5 SMCLK SMBus clock JTAG2 TCK 6 SMDAT SMBus data JTAG3 TDI 7 GND Ground JTAG4 TDO 8 +3.3V 3.
6.3 Ethernet and TAP RJ-45 interface Two 100Mbit/s full duplex ports are available in ERTEC 200P. PHYs are integrated in ERTEC 200P package. Only external magnetics with RJ45 connector are necessary for PROFINET functionality. In the following table pin out of both wired Ethernet ports is described.
6.4 Sync connector For synchronization measurement the BNC connector is assembled and alternatively the 3 pin connector as assembly option. Signals on 3pin connector are RS485 signals. In the following table pin outs of sync connectors are described. Connector name: X2 Connector type: BNC Signal BNC Pin Signal Tip Sync In/Out*1 Shield GND 1 Sync RS485 P 3 pin connector 2 Sync RS485 N 3 GND via100k Table 22 Pin assignment of external synchronization connector Note: 6.
Signal Pin Pin D16 37 38 D0 Signal D17 35 36 D1 D18 33 34 D2 D19 31 32 D3 D20 29 30 D4 D21 27 28 D5 D22 25 26 D6 D23 23 24 D7 D24 21 22 D8 D25 19 20 D9 D26 17 18 D10 D27 15 16 D11 D28 13 14 D12 D29 11 12 D13 D30 9 10 D14 D31 7 8 D15 XBE0 5 6 XBE1 +3.3V 3 4 +3.3V +3.3V 1 2 +3.3V GND GND 1 GND 2 GND GND GND 3 GND 4 GND GND GND 5 Table 24 Pin assignment of EMC connector X80 Copyright © Siemens AG 2013.
Signal Pin Pin A16 37 38 A0 Signal A17 35 36 A1 A18 33 34 A2 A19 31 32 A3 A20 29 30 A4 A21 27 28 A5 A22 25 26 A6 A23 23 24 A7 XCS_PER0 21 22 A8 XCS_PER2 19 20 A9 XCS_PER3 17 18 A10 XWR 15 16 A11 XRD 13 14 A12 XRDY_PER 11 12 A13 DTXR 9 10 A14 XOE_DRIVE 7 8 A15 XBE2 5 6 XBE3 +3.3V 3 4 +5V +3.
Signal ERTEC GPIO Pin GND 1 GND 2 GPIO0 3 GPIO0 GPIO1 4 GPIO1 GPIO2 5 GPIO2 GPIO3 6 GPIO3 GPIO4 7 GPIO4 GPIO5 8 GPIO5 GPIO6 9 GPIO6 GPIO7 10 GPIO7 GPIO8 11 GPIO16 GPIO9 12 GPIO17 GPIO10 13 GPIO18 GPIO11 14 GPIO19 GPIO12 15 GPIO20 GPIO13 16 GPIO21 GPIO14 17 GPIO22 GPIO15 18 GPIO23 +3.3V 19 +3.3V 20 Table 26 Pin assignment of GPIO connector X50 6.8 JTAG connector for FPGA For programming a 10 pin JTAG connector is assembled.
Signal Pin Pin GPIO16 37 38 GPIO0 Signal GPIO17 35 36 GPIO1 GPIO18 33 34 GPIO2 GPIO19 31 32 GPIO3 GPIO20 29 30 GPIO4 GPIO21 27 28 GPIO5 GPIO22 25 26 GPIO6 GPIO23 23 24 GPIO7 GPIO24 21 22 GPIO8 GPIO25 19 20 GPIO9 GPIO26 17 18 GPIO10 GPIO27 15 16 GPIO11 GPIO28 13 14 GPIO12 GPIO29 11 12 GPIO13 GPIO30 9 10 GPIO14 GPIO31 7 8 GPIO15 NC 5 6 NC +3.3V 3 4 +5V +3.
Table 29 Pin assignment of GPIO connector X21 Signal Pin Pin Signal GPIO80 37 38 GPIO64 GPIO81 35 36 GPIO65 GPIO82 33 34 GPIO66 GPIO83 31 32 GPIO67 GPIO84 29 30 GPIO68 GPIO85 27 28 GPIO69 GPIO86 25 26 GPIO70 GPIO87 23 24 GPIO71 GPIO88 21 22 GPIO72 GPIO89 19 20 GPIO73 GPIO90 17 18 GPIO74 GPIO91 15 16 GPIO75 GPIO92 13 14 GPIO76 GPIO93 11 12 GPIO77 GPIO94 9 10 GPIO78 GPIO95 7 8 GPIO79 NC 5 6 NC +3.3V 3 4 +5V +3.
Signal Pin Pin TRACEPKT8 37 38 PIPESTAT0 Signal TRACEPKT9 35 36 PIPESTAT1 TRACEPKT10 33 34 PIPESTAT2 TRACEPKT11 31 32 TRACESYNC TRACEPKT12 29 30 TRACEPKT0 TRACEPKT13 27 28 TRACEPKT1 TRACEPKT14 25 26 TRACEPKT2 TRACEPKT15 23 24 TRACEPKT3 TRST- 21 22 TRACEPKT4 TDI 19 20 TRACEPKT5 TMS 17 18 TRACEPKT6 TCK 15 16 TRACEPKT7 RTCK 13 14 JTAG-VTREF TDO 11 12 ETM-VTREF SRST- 9 10 EXTRIG DBGRQ 7 8 DBACK NC 5 6 TRACECLK NC 3 4 NC NC 1 2 NC GN
6.12 Configuration pins for ERTEC 200P For this purpose a double row 2x15 SMD pin header with RM 2.54mm (mechanically is this pin header composed from 2x10 and 2x5 pin header) is assembled. Boot configuration is described in the following table.
Jumper configuration for selecting ERTEC configuration is described in the following table.
Function F_XHIF(3) F_XHIF(2) F_XHIF(1) F_XHIF(0) Close Open x Close XHIF=16bit, XHIF_XWR = R/W XHIF=16bit, XHIF_XWR, XHIF_XWR separated Close Open x Open XHIF=16bit, XHIF_XRDY active high Close Open Open x XHIF=16bit, XHIF_XRDY active low Close Open Close x XHIF=32bit, XHIF_XWR = R/W XHIF=32bit, XHIF_XWR, XHIF_XWR separated Close Close x Close Close Close x Open XHIF=32bit, XHIF_XRDY active high Close Close Open x XHIF=32bit, XHIF_XRDY active low Close Close Close x Remai
Test and debug circuits configuration pin header pin out is described in the following table.
7 Settings on the EB 200P Two connectors for various settings are integrated in the EB 200P. These are used to specify various modes and selections of function groups on the EB 200P: o o o Selection of boot medium and boot software Selection of the ERTEC 200P configuration Activation/deactivation of different board functions The exact position of the two connectors is shown schematically in Section 6. Following picture shows the default configuration of the ERTEC 200P.
JTAG FPGA Following picture shows the default configuration of the EB 200P FPGA and onboard peripheral circuits. More information about each jumper functionality is in chapter 6.13 . Figure 7 EB 200P default configuration of onboard circuits Copyright © Siemens AG 2013. All rights reserved. Technical data subject to change 43 EB 200P Manual Version 1.0.
8 Structure of the EB 200P 8.1 Mechanical Structure The EB 200P is a PCI Express card where the main mechanical component is PCB. 8.2 Front and Display Element Figure 8 EB 200P slot bracket view 8.3 Description of LEDs on the slot bracket On the slot bracket, there are four LEDs available. Following is the functionality of each LED.
9 Miscellaneous 9.
9.2 References: Datasheet_ERTEC200P_V1.0.pdf Manual_ERTEC200P_V1.0.pdf Guideline_EvalKit_ERTEC200P_V4.0.0.pdf Technical Reference Manual ARM926EJ-S Part 1 Technical Reference Manual ARM926EJ-S Part 2 Embedded Trace Macrocell Architecture Specification (ETM_Spec.PDF); Multi-ICE System Design Consideration Applic.-Note 72 (DAI0072A_Multiicedesign-Notes.PDF); IEEE Standard Test Access Port and Boundary-Scan Architecture (1149.1 IEEE Boundary Scan 2001.PDF); /9/ ETM9 Technical Reference Manual (Rev.
