Technical data

7.9 JTAG Interface
For connecting a debugger or ICE.
Connector name: X61
Connector type: 2x10-pin male connector
Pin No. Signal Name Function
1 VTREF 3.3 V reference voltage
2 VSUPPLY 3.3 V
3 TRST_N JTAG reset
4 M Ground
5 TDI JTAG data in
6 M Ground
7 TMS JTAG test mode select
8 M Ground
9 TCK JTAG test clock
10 M Ground
11 Not used (RTCK) Synchronous JTAG clock (not used in ERTEC 200)
12 M Ground
13 TDO JTAG Test Data Out
14 M Ground
15 SRST_N System Reset
16 M Ground
17 Not used (DBREQ) Default not used with test board
18 M Ground
19 Not used (DBGACK) Default not used with test board
20 M Ground
Table 24: Pin Assignment of JTAG Interface
7.10 JTAG Programming Interface for FPGA (Byte Blaster)
JTAG interface for interfacing of PCI-FPGAs.
Connector name: X62
Connector type: 2x5-pin male connector
Pin No. Signal Name Function
1 TCK JTAG test clock
2 M Ground
3 TDO JTAG data out
4 VSUPPLY 3.3 V
5 TMS JTAG test mode select
6 - -
7 - -
8 - -
9 TDI JTAG data in
10 M Ground
Table 25: Pin Assignment for Byte Blaster FPGA Programming Interface
Copyright © Siemens AG 2010. All rights reserved. 39 EB 200 Manual
Technical data subject to change Version 1.1.4