Technical data

6 Settings on the EB 200
This section describes different register groups and the parameters of the CPLDs that are specified by default on the
EB 200.
6.1 Default Settings of the EMIF Interface
The following settings are made on the registers of the External Memory Interface. The ERTEC 200 registers are
described in document /2/.
Register Address Date Comment
Async wait cycle config 0x7000_0004 0x4000_0080 RDY_PER_N = 1; Max_Ext_Wait =
128 (0x80) x 16 = 2048 AHB cycles
SDRAM Bank Config 0x7000_0008 0x0000_0521 9CAS, 13RAS, 2CAS Delay
SDRAM Refresh Control 0x7000_000C 0x0000_0320 Refresh every 8 us
ASYNC Bank0 Config 0x7000_0010 0x0462_2311 16-bit, 120 ns RD&WR, 20 ns setup &hold
ASYNC Bank1 Config 0x7000_0014 0x0462_2311 16-bit, 120 ns RD&WR, 20 ns setup &hold
ASYNC Bank2 Config 0x7000_0018 0x0462_2312 32-bit, 120 ns RD&WR, 20 ns setup &hold
ASYNC Bank3 Config 0x7000_001C 0x0462_2312 32-bit, 120 ns RD&WR, 20 ns setup &hold
Extended Config 0x7000_0020 0x0303_0000 Default value
Table 11: Default Settings of EMIF Registers on the EB 200
Copyright © Siemens AG 2010. All rights reserved. 28 EB 200 Manual
Technical data subject to change Version 1.1.4