Technical data

3 Memory Allocation of EB 200
This section describes the address space of the EB 200 from the standpoint of the four AHB masters.
The table below shows the possible accesses of the master to the slaves.
AHB Master-Slave Coupling
Slave
Master
APB
Slave 1
EMIF
Slave 2
DMA
Slave 3
IRT
Slave 4
INT Control
Slave 5
ARM X X X X X
IRT X
DMA X X
LBU X X X
Table 8: Overview of AHB Master-Slave Access
3.1 Memory Mapping
The four AHB masters of the ERTEC 200 use the memory area differently. The table below shows the memory
segments used:
Start and
End
Address
Seg.
Function Area for
ARM9
Function Area for
IRTE
Function Area for
LBU
Function Area for
DMA
0000 0000
0FFF FFFF
0
Boot ROM(0-8 KB)
EMIF-SDRAM
(0-128 MB)
EMIF memory
(0-64 MB)
D-TCM (4 KB)
locked I-cache(2/4/6
KB)
Boot ROM(0-8 KB)
EMIF-SDRAM
(0-128 MB)
EMIF memory
(0-64 MB)
Boot ROM(0-8 KB)
EMIF-SDRAM
(0-128 MB)
EMIF memory
(0-64 MB)
Boot ROM(0-8 KB)
EMIF-SDRAM
(0-128 MB)
EMIF memory
(0-64 MB)
1000 0000
1FFF FFFF
1
IRT switch
controller
IRT switch
controller
IRT switch
controller
Not used
2000 0000
2FFF FFFF
2 EMIF (SDRAM) EMIF (SDRAM) EMIF (SDRAM) EMIF (SDRAM)
3000 0000
3FFF FFFF
3
EMIF (Area: Bank
0-3)
EMIF (Area: Bank
0-3)
EMIF (Area: Bank
0-3)
EMIF (Area: Bank
0-3)
4000 0000
4FFF FFFF
4
All APB macros
incl. boot ROM
Not used
All APB macros
incl. boot ROM
All APB macros
incl. boot ROM
5000 0000
5FFF FFFF
5 ARM-ICU Not used Not used Not used
6000 0000
6FFF FFFF
6 Not used Not used Not used Not used
7000 0000
7FFF FFFF
7 EMIF register Not used EMIF register Not used
8000 0000
8FFF FFFF
8 DMA Not used Not used Not used
9000 0000
FFFF FFFF
9 - 15 Not used Not used Not used Not used
Table 9: Function Groups with Memory Segments Used
Copyright © Siemens AG 2010. All rights reserved. 23 EB 200 Manual
Technical data subject to change Version 1.1.4