Technical data

2.3 CPLD Interface
One Lattice type LC4256C CPLD is integrated on the EB 200. The following functions are implemented with these
CPLD:
 Serial memory block control, boot/normal operation
 Connection and selection of boot configuration
 Connection and selection of system configuration
 Generation of the different boot chip selects
 Forwarding of Ethernet controller interrupts
 Ready adaptation for external LAN interface
 Hardware revision level
The CPLD can be programmed with the JTAG interface X63 (for description, refer to Section 7.11).
2.4 Reset System of the EB 200
The reset system of the EB 200 has 3 reset paths:
 Power On Reset:
This reset is generated during power up and with the integrated reset button on the EB 200. The RESET_N signal
affects the following function units.
 Resetting of ERTEC 200 logic except for the PCI/LBU side
 Output PHY_RES_N is activated  Discrete PHYs are reset
 Output SRST_N is activated  Debug logic is reset
 Output RESET_N is wired to I/O slot
 Host – Reset:
If the EB 200 is operated with an active host, the connected host reset acts the same as the RESET_N signal.
The effects of the host reset are the same as for the power-on reset.
 Resetting the Debug Interface:
The debug interface is linked to the two reset signals SRST_N and TRST_N of the EB 200. This enables the
debugger to initiate and monitor the reset of the following function groups.
 Resetting of ERTEC 200 logic except for the host side (LBU interface)
 Output PHY_RES_N is activated  Discrete PHYs are reset
The hardware reset remains active for at least 20 ms following power up.
Reset
Controller
1
1
ERTEC
200
TRST_N
RESET_N
SV
5 V / 3.3 V
JTAG Interface
PORES_N
SV
3.3 V/1.5 V
Reset
Button
PCI Interface
3.3 V
LBU Slot
MII Ethernet
phys
I/O Slot
SRST_N RES_PHY_N
Figure 3: Reset Logic of the EB 200
Copyright © Siemens AG 2010. All rights reserved. 20 EB 200 Manual
Technical data subject to change Version 1.1.4