Technical data

FIQ # BLOCK
SOURCE
SIGNAL DEFAULT COMMENT
0 Watchdog Rising edge Watchdog 0 – timer has expired
1 APB_Bus Rising edge Access to non-existing address on the APB
2 Multilayer_AHB Rising edge Access to non-existing address on the
AHB
3 PLL Stat
Register in
SCRB
Rising edge Group interrupt of:
- I/O QVZ (EMIF: memory controller)
- PLL loss state
- PLL lock state
See system control register
PLL_STAT_REG
4 ARM processor COMMRX Rising edge Interrupt for comm channel (receive)
5 ARM processor COMMTX Rising edge Interrupt for comm channel (transmit)
6 Optional Optional
IRQ[15:0]
Rising edge User-programmable IRQ source
7 Optional Optional
IRQ[15:0]
Rising edge User-programmable IRQ source
Table 4: FIQ Interrupts
2.1.8 External Memory Interface (EMIF)
SDRAMs, SRAMs, and any I/O blocks can be connected to the external memory interface. In total, 5 chip-select lines
are available:
 1 CS line for SDRAM with 16/32-bit data width
 4 CS lines for asynchronous memory and I/O with 8/16/32-bit data width and assignable timing
The EB 200 has a socketed boot Flash to enable a simple firmware update in stand-alone mode. The boot medium is
always expected on chip select signal CS_PER0_N. The socketed boot Flash is addressed with CS_PER0_N by
means of boot jumper J2 = “External ROM 8-bit data width" (see Section 8). The 4-Mbyte firmware Flash is then
selecte
d with CS_PER1_N. If the EB 200 is operated with a debugger (ICE), the boot Flash can be omitted as the
firmware Flash can be programmed directly. The following blocks of the EB 200 can be selected with the chip-select
lines:
Chip Select I/O Function
Flash-Boot 8 Bit Flash-Boot 16 Bit
CS_PER0_N Boot Flash / FLASH 512 Kbytes (8-bit)
fixed wait states
4 Mbytes (16-bit)
fixed wait states
CS_PER1_N FLASH / SRAM 4 Mbytes (16-bit)
fixed wait states
8 Mbytes (32-bit)
fixed wait states
CS_PER2_N CPLD, Ethernet, external
I/O
16 Mbytes (32-bit) fixed wait states
CS_PER3_N FPGA for accesses to the
PC host system
16 Mbytes (32-bit) ready timing
CS_SDRAM_N SDRAM 64 Mbytes
Table 5: CS Areas of the EB 200
The size of the chip select areas of CS_PER0_N - CS_PER3_N is defined as 16 Mbytes. The memory areas indicated
above appear mirrored correspondingly often.
The SDRAM can be regarded functionally as a dual-port RAM because the LBU interface, IRT switch, and
ARM946E_S all have access to the memory due to the multimaster capability of the ERTEC 200.
Copyright © Siemens AG 2010. All rights reserved. 15 EB 200 Manual
Technical data subject to change Version 1.1.4