Technical data

2.1.4 ERTEC 200 Processor and I/O
The ARM946E-S processor with interrupt controller is integrated in the ERTEC 200. The processor and various
standard I/O are available to users for their applications. These include the following function groups:
 ARM946E-S processors with
 50/100/150 MHz operating frequency that can be set via jumpers (see Operating Modes 2.1.2)
 8 Kbytes of instruction cache
 4 Kbytes of data cache
 4 Kbytes of data TCM
 JTAG interface for debug interface
 Interrupt controller for asynchronous events (16 IRQ and 8 FIQ inputs)
 SDRAM controller 50 MHz/max. 128 Mbytes of address space (16/32-bit data width can be assigned)
 SRAM controller, up to 4 x 16 Mbytes (8/16/32-bit data width and timing can be assigned separately for all 4
areas)
 Watchdog timer unit for monitoring module functions
 Timer unit for generating periodic trigger pulses
 F-timer for fail-safe applications
 GPIO ports for activating LEDs, etc.
 SPI interface for connecting serial EEPROM/Flash
 UART
2.1.5 PCI Interface
A PCI bridge enabling connection to a PCI bus is integrated in the ERTEC 200 by means of an FPGA. However, the
PCI interface is used only for the function test of the EB 200.
2.1.6 IRT switch
The IRT switch provides the required function for PROFINET IO. It contains the following functions:
 Configuration register for IRT switch
 64 Kbytes of K-RAM for RT and IRT communication
The IRT switch functions are described in document /3/.
2.1.7 Interrupt System of the EB 200
The EB 200 has two interrupt controller units that can only be operated by the ARM946E-S.
 IRQ controller unit with 16 inputs for low-priority interrupts
 FIQ controller unit with 8 inputs for high-priority interrupts
The IRQ/FIQ interrupt sources are listed in the tables below.
INTERRUPT # BLOCK
SOURCE
SIGNAL DEFAULT COMMENT
0 Timer0 TIM_INT0 Rising edge Timer 0
1 Timer1 TIM_INT1 Rising edge Timer 1
3:2 GPIO GPIO1/0 Assignable ERTEC 200 pins GPIO_IO[1:0]
5:4 GPIO GPIO31/30 Assignable ERTEC 200 pins GPIO_IO[31:30]
6 Timer2 TIM_INT2 Rising edge Timer 2
7 -- -- -- Reserved
8 UART UARTINTR High level Group interrupt UART
9 PHY0/1 P1/2_INTERP Rising edge Interrupt from PHY1/2
10 SPI1 SSPINTR Rising edge SPI1 group interrupt
11 SPI1 SSPRORINTR Rising edge SPI Receive overrun interrupt
12 IRT switch
control
IRQ0_SP Rising edge High-priority IRTE interrupt
13 IRT switch
control
IRQ1_SP Rising edge Low-priority IRTE interrupt
14 -- -- -- Reserved
15 DMA DMA_INTR Rising edge DMA controller, DMA transfer complete
Table 3: IRQ Interrupts
Copyright © Siemens AG 2010. All rights reserved. 14 EB 200 Manual
Technical data subject to change Version 1.1.4