Technical data

2.1.2 Operating Modes of the EB 200
Various configurations on the EB 200 can be set by means of jumpers X10.9/10 to X11.3/4. These jumpers are
described in Section 8. The following configuration settings are possible on the ERTEC 200.
CONFIG[6]
X11 3/4
CONFIG[5]
X11 1/2
CONFIG[4]
X10 15/16
CONFIG[3]
X10 13/14
CONFIG[2]
X10 11/12
CONFIG[1]
X10 9/10
Meaning
- - - - - 1
REF_CLK tristate
- - - - - 0
REF_CLK output (25 MHz)
- 1 - - 0 -
LBU = On  LBU-CFG:
LBU_WR_N has read/write
control
- 0 - - 0 -
LBU = On  LBU-CFG:
Separate read and write line
1 - - - 0 -
LBU = On  LBU_POL_RDY:
LBU_RDY_N is high-active
0 - - - 0 -
LBU = On  LBU_POL_RDY:
LBU_RDY_N is low-active
0 1 - - 1 -
LBU = Off  GPIO44-32 = On
int. PHYs = On, ext. MII = PHY
debugging, ETM9 = Off
1 0 - - 1 -
LBU = Off  GPIO44-32 = On
int. PHYs = On, ext. MII = Off,
ETM9 = On
1 1 - - 1 -
LBU = Off  GPIO44-32 = On
int. PHYs = Off, ext. MII = On,
ETM9 = Off
- - 0 0 - -
ARM clock 50 MHz
- - 0 1 - -
ARM clock 100 MHz
- - 1 0 - -
ARM clock 150 MHz
- - 1 1 - - Reserved
 LBU mode: CONFIG[2] = 0
The LBU interface is active for access of a host processor system to internal components of the ERTEC 200. The
internal PHYs are used in this operating mode. Debugging of internal PHYs and diagnostics via the trace
interface are not possible in this mode.
 MII diagnostics: CONFIG[2] = 1; CONFIG[5] = 1; CONFIG[6] = 0;
Diagnostics of the signals between internal PHYs and IRT switch is possible in this mode. The GPIO[44:32] is
also available.
 Trace mode: CONFIG[2] = 1; CONFIG[5] = 0; CONFIG[6] = 1;
The trace port and the GPIO[44:32] are available to the user in this mode.
X11 5/6
Meaning
1
SPI Boot Mode 1 (EEPROM)
SPI_CONFIG
0
SPI Boot Mode 2 (Flash)
Copyright © Siemens AG 2010. All rights reserved. 12 EB 200 Manual
Technical data subject to change Version 1.1.4