Technical data
2 Hardware Structure of the EB 200
2.1 ERTEC 200
2.1.1 Function Overview
Refer to documents /1/ and /2/ for a detailed function description of the ERTEC 200.
In this manual, only the main components are described briefly and represented in a block diagram.
The following four AHB masters are integrated in the ERTEC 200:
ARM946E-S with trace/debug port and high-performance interrupt controllers
IRT switch with 64 Kbytes of K-RAM for real-time Ethernet communication
External host processor on the LBU interface
Single channel DMA controller
The following I/O blocks are available to the masters:
External memory interface (EMIF) with SDRAM and SRAM controller
Two Ethernet interfaces with integrated MII PHYs
I/O via APB bridge
45-bit GPIO
UART
SPI
3 timers
F-timer
Watchdog
Boot ROM
System function register
The multi-layer AHB bus system enables a largely independent operation of the masters. An internal arbitration logic
prevents access conflicts if multiple masters want to access the same I/O block. The function groups of the ERTEC
200 are shown in the following block diagram:
DMA-
C o ntrolle r
AHB/APB
Bridge
GPIO
Master
Master
P
P
o
r
t
s
7
APB
50MHz / 32 Bit
74
LB U / M II + S M I /
ETM / GPIO
1 x UART
SPI1
Inte rface
3 x Timer,
W atchdog,
F-Timer
ARM9
clock
50MHz
100MHz
1
1
25MHz
SC-Bus (5 0 M H z )
32 Bit
2-Port Switch
Switch Control
K-SRAM
64 kByte
Ethernet-
Kanal
(Port 0)
Ethernet-
Kanal
(Port 1)
21
20
32
5
GPIO,
UART,
SPI,
Timer,
W atchdog,
PHY0
AHB-
W rapper
Slave
Master
Slave
Slave
2
Slave
Boot-
ROM
(8 kByte)
Slave
32
8
1
Test
Multi-Layer-AHB
50 MHz/32Bit
Memory-
C o n trolle r
(EM IF)
Slave
Input
stage
MUX/Arb.
MUX/Arb.
MUX/Arb.
4
Reset
System
Control
Clock-Unit
F_CLK
48
Local
Bus Unit
16 Bit
(LB U )
Master
Inp ut
stage
MUX
ERTEC200
MC-PLL Signals
PHY
(Port 0)
PHY
(Po rt 1)
ARM946ES
with
I-C a ch e
(8kByte ),
D-Cache
(4kByte),
D-TCM
(4kByte)
Master
7
BS-
TAP
JTA G / D ebug
AHB-
Wrapper
Master
MC-Bus (5 0M H z)
32 Bit
Slave
Input
stage
ARM-
Interrupt-
Controller
Slave
Decode
Input
stage
Slave
Decode
1
MII-0
MII-1
PLL
48
SMI
3
16
16
External
M em ory Interfa ce
PHY1
1
REF_
CLK
ETM
Inte rfa c e
TRACE_
CLK
14
1
13
13
Slave Slave Slave
Figure 2: ERTEC 200 Block Diagram
Copyright © Siemens AG 2010. All rights reserved. 11 EB 200 Manual
Technical data subject to change Version 1.1.4