EB 200 . Evaluation Board ERTEC 200 Manual Copyright © Siemens AG 2010. All rights reserved. Technical data subject to change Page 1 EB200 Manual Version 1.1.
Edition (10/2010) Disclaimer of Liability We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly. Necessary corrections are included in subsequent editions. Suggestions for improvement are welcomed. Copyright © Siemens AG 2010.
Preface Contents of this Manual Detailed description of the individual function groups of the EB 200 Connector pin assignment and jumper assignment Target Audience of this Manual This manual is intended for hardware developers who want to use the ERTEC 200 for new products. Experience working with processors and designing embedded systems and knowledge of Ethernet are required for this. The manual serves as a reference for software developers.
Guide To help you quickly find the information you need, this manual contains the following aids: o A complete table of contents as well as a list of all figures and tables in the manual are provided at the beginning of the manual. o A glossary containing definitions of important terms used in the manual is located following the appendices. o References to other documents are indicated by the document reference number enclosed in slashes (/No./).
Contents 1 Introduction.............................................................................................................................8 1.1 1.2 1.3 1.4 2 Procedure when Using ERTEC 200 to Develop Your Own PROFINET IO Device ................................ 8 Structure of the EB 200 .......................................................................................................................... 9 Features of the EB 200.................................................................
7.10 JTAG Programming Interface for FPGA (Byte Blaster) .......................................................................... 39 7.11 CPLD Programming Interface ................................................................................................................ 40 8 Settings on the EB 200 ..........................................................................................................40 8.1 Boot/Configuration Connector X10..........................................................
List of Figures Figure 1: Block Diagram of the EB 200......................................................................................................................... 10 Figure 2: ERTEC 200 Block Diagram ........................................................................................................................... 11 Figure 3: Reset Logic of the EB 200 .............................................................................................................................
1 Introduction This manual describes the procedure for using the ERTEC 200 for HW development of a PROFINET IO device and the properties of the EB 200 evaluation board. The intended use of the EB 200 evaluation board is as follows: It serves as a template for development of your own PROFINET IO device hardware. It supports development and testing of your own PROFINET IO device application software.
1.2 Structure of the EB 200 The EB 200 is implemented in the form of a PCI card. The PCI interface is used only for module tests. In standard configuration the EB 200 is operated as a stand-alone module. The EB 200 is supplied by means of an external plugin power supply (part of the development kit). For debugging the Amontec JTAG debugger including usb cable (both also part of the development kit) can be plugged onto the EB200 as shown in the following picture. 1.
1.4 Block Diagram of the EB 200 SYNC External Supply Supply 3,3V 1,5V Debugger I/O Slot for Expansion SPI 25 MHz TX 2xRJ45 with int.
2 Hardware Structure of the EB 200 2.1 ERTEC 200 2.1.1 Function Overview Refer to documents /1/ and /2/ for a detailed function description of the ERTEC 200. In this manual, only the main components are described briefly and represented in a block diagram.
2.1.2 Operating Modes of the EB 200 Various configurations on the EB 200 can be set by means of jumpers X10.9/10 to X11.3/4. These jumpers are described in Section 8. The following configuration settings are possible on the ERTEC 200.
X11 Pin 13,14 SYS_Config[4] SYS_Config[3] SYS_Config[2] SYS_Config[1] SYS_Config[0] Meaning LBU Mode - - Pin 11,12 - Pin 9,10 0 Pin 7,8 Open = 1 For = 0 Pin 15,16 0 LBU On internal PHY’s = on external MII = off ETM-Trace = off GPIO 32-44 = off PHY debugging - - - 1 0 LBU = Off Internal PHYs = On External MII = PHY debugging ETM trace = Off GPIO 32-44 = On Trace mode - - - 0 1 0 1 0 1 - 0 1 - 1 - 1 - LBU = Off Internal PHYs = On External MII = Off ETM trace = On GPIO 32-44 = On
2.1.4 ERTEC 200 Processor and I/O The ARM946E-S processor with interrupt controller is integrated in the ERTEC 200. The processor and various standard I/O are available to users for their applications. These include the following function groups: ARM946E-S processors with 50/100/150 MHz operating frequency that can be set via jumpers (see Operating Modes 2.1.
FIQ # BLOCK SOURCE 0 1 2 SIGNAL DEFAULT COMMENT Watchdog APB_Bus Multilayer_AHB Rising edge Rising edge Rising edge 3 PLL Stat Register in SCRB Rising edge 4 5 6 ARM processor ARM processor Optional Rising edge Rising edge Rising edge Watchdog 0 – timer has expired Access to non-existing address on the APB Access to non-existing address on the AHB Group interrupt of: - I/O QVZ (EMIF: memory controller) PLL loss state PLL lock state See system control register PLL_STAT_REG Interrupt for comm ch
2.1.9 Debug and Trace Interface The ETM macro cell of the ARM946E-S can be used as a debug and trace interface in the ERTEC 200. With this interface, the user software running on the ARM946E-S and the user data can be analyzed and traced. The ETM module is a standard module recommended by ARM on which various available debuggers can be run. If the trace interface is used, the LBU interface is not available (configuration setting "Trace On“, see Section 2.1.2).
Signal Name Function 1 GPIO21 GPIO22 Alternative Function 2 Alternative Function 3 Alternative Function 4 Use (Default) SPI1_SFRMOUT SPI1_SFRMIN DBGACK GPIO GPIO GPIO23 SPI_SCLKIN The GPIO is used as chip select for SPI-Data-Flash or SPI-EEPROM if SPI Bootmode is selected (setting see Table 2) IRT-SYNC Direction (O) (RS485) GPIO24 PLL_EXT_IN_N IRT-SYNC Input GPIO25 TGEN_OUT1_N IRT-SYNC Output GPIO26 TGEN_OUT2_N GPIO GPIO27 TGEN_OUT3_N GPIO GPIO28 TGEN_OUT4_N GPIO GPIO29 TGEN_OUT5_N
Signal Name Function 1 LBU Config(6,5,2) = xx0b LBU_A16 LBU_A17 LBU_A18 LBU_A19 LBU_A20 LBU_SEG_0 LBU_SEG_1 LBU_CS_R_N Alternative Function 2 PHY-Debug Config(6,5,2) = 011b GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 Alternative Function 3 ETM -Trace Config(6,5,2) = 101b GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 Alternative Function 4 Reserved Config(6,5,2) = 111b IO Function (Reset): see Config (6,5,2)) I/B/B (GPIO:I) I/B/B (GPIO:I) I/B/B (GPIO:I) I/B/B (GPIO:I) I/B/B (GPIO:I
2.2 Memory on EB 200 The following memory types are available on the EB 200 evaluation board: 2.2.1 SDRAM Interface The SDRAM interface consists of 2 Infineon type HYP39S25616DT-7.5 blocks. 64-Mbyte memory capacity 32-bit data width 50 MHz clock frequency 2.2.2 SRAM Interface The SDRAM interface consists of 2 Samsung type KF3216U6M-EF700000 blocks. 8-Mbyte memory capacity 32-bit data width 2.2.3 Flash Interface Two different Flash types are used for the Flash interface: 1.
2.3 CPLD Interface One Lattice type LC4256C CPLD is integrated on the EB 200.
2.4.1 Reset Button The EB 200 has a reset button that initiates a manual reset of the EB 200 without disconnecting the voltage supply. 2.4.2 PCI Reset During PCI mode, the host reset controls the evaluation board directly. 2.4.3 Watchdog and Software Reset Additional reset events can be initiated by the watchdog or a software reset. Both reset events have the same effect as a debug reset. 2.5 Clock System of the EB 200 2.5.
2.6 Ethernet Interface of the EB 200 The EB 200 Ethernet interface is implemented as a double electrical interface (Tx). The PHYs have the following functionality: Transfer rate 100 Mbits Full duplex MDI/ MDI-X autocrossover Autopolarity Link and Activity LED functionality After reset of the EB 200, the PHYs are inactive and must first be activated via the software. The PHYs are connected to two RJ45 Ethernet sockets via a transformer.
3 Memory Allocation of EB 200 This section describes the address space of the EB 200 from the standpoint of the four AHB masters. The table below shows the possible accesses of the master to the slaves. Slave AHB Master-Slave Coupling Master APB Slave 1 EMIF Slave 2 DMA Slave 3 IRT Slave 4 INT Control Slave 5 ARM X X X X X IRT X DMA X X LBU X X X Table 8: Overview of AHB Master-Slave Access 3.1 Memory Mapping The four AHB masters of the ERTEC 200 use the memory area differently.
The D-TCM with a maximum size of 4 Kbytes can be displayed on any aligned address area. The ARM946E-S then accesses the D-TCM under this address and not the AHB bus. In addition, the locked I-cache of 2/4/6 Kbytes can be displayed on any aligned address area. Only the ARM946E-S can access both address areas. IRT accesses to the KRAM do not use the AHB bus. These accesses are implemented in the IRT switch controller. The KRAM can be addressed starting from the memory area 0x1010_0000.
Segment Contents Size Address Area Timer 0 - 2 256 bytes 4000_2000 4000_20FF 32 bytes, physical; Watchdog 256 bytes 4000_2100 4000_21FF 28 bytes, physical; SPI 256 bytes 4000_2200 4000_22FF 256 bytes, physical; UART1 256 bytes 4000_2300 4000_23FF 256 bytes, physical; Not used 256 bytes 4000_2400 4000_24FF 256 bytes, physical; GPIO 256 bytes 4000_2500 4000_25FF 32 bytes, physical System control register block 256 bytes 4000_2600 4000_26FF 164 bytes, physical System register blo
4 Operating Modes of the EB 200 The EB 200 is operated in stand-alone mode. An external plug-in power supply on connector is used to supply the module with regulated voltage of 6 to 9 V/1.5 A. 4.1 Operating the EB 200 without programmed Flash This mode is used, for example, when the EB 200 evaluation board is operated with a debugger. When the EB 200 is switched on, the debugger assumes control of the EB 200.
5 JTAG Interface Several functions of the module can be performed with the JTAG interface of the EB 200. Debugging of the EB 200 on connector X61 (see circuit 1) Boundary scan of all boundary scan-capable ICs on connector X61 (see circuit 1) The debugging or boundary scan selection is specified with the ERTEC 200 input TAP SEL. TAP_SEL = High BS disable Debugging selected. TAP_SEL = Low BS enable Boundary scan selected.
6 Settings on the EB 200 This section describes different register groups and the parameters of the CPLDs that are specified by default on the EB 200. 6.1 Default Settings of the EMIF Interface The following settings are made on the registers of the External Memory Interface. The ERTEC 200 registers are described in document /2/.
7 Connectors of the EB 200 The following connectors are available on the EB 200 for the interface connection to external components and systems. o o o o o o o o o o o o o PCI Interface External DC power supply 2 Ethernet downlink interface Reserved UART GPIO [15 to 0] GPIO [31 to .16] GPIO [44 to .
7.1 PCI Interface The PCI interface corresponds to the standardized PCI interface. The PCB direct connector has the 5V universal card characteristic. The PCI interface is used only for the function test of the EB 200. Connector name: X1 Connector type: 124-pin PCB direct connector Pin No.
B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 AD[08] AD[07] +3.3 V AD[05] AD[03] M AD[01] +Vio ACK64_N +5 V +5 V Key Address/data Address/data Supply Address/data Address/data Ground Address/data I/O supply Acknlg64 from master Supply Supply A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 CBE_N[0] +3.
7.2 LBU Interface Instead of the PCI interface, the PCB direct connector can also be used for the LBU interface (see jumper settings in chapterl 2.1.2). In this case, the following signal assignment applies: Connector name: X1 Connector type: 124-pin PCB direct connector Pin No.
B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 M LBU_DB12 LBU_DB10 M LBU_DB08 LBU_DB07 +3.3 V LBU_DB05 LBU_DB03 M LBU_DB01 +Vio +5 V +5 V Ground 12-bit data bus 10-bit data bus Ground Key Key 8-bit data bus 7-bit data bus Supply 5-bit data bus 3-bit data bus Ground 1-bit data bus I/O supply Reserved Supply Supply A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 LBU_DB13 LBU_DB11 M LBU_DB09 LBU_BE0_N +3.
7.4 Double Ethernet Switch Two RJ45 sockets with integrated magnetics are used in EB 200. The assignment of each socket corresponds to that of a switch (downlink). The integrated magnetics support autocrossover – MDI/MDIX. Connector name: X3, X4 Connector type: RJ45 socket with integrated LEDs Connector assignment: Switch (downlink) Pin No.
7.6 GPIO Interface The GPIO[44 :0] are available to the user by means of three plug connectors X20-X22. In addition, the boundary scan enable signal is also located on connector X20.
Note: The GPIO[44:32] are only available as Inputs on EB200 if Alternativfunctions 2 or 3 are selected.
Connector name: X31 Connector type: 2x13-pin plug connectors Pin No. Signal Name Function 1 P3V 3.
7.8 Trace Interface For connecting a trace interface to the ETM macro cell of the ARM946E-S Connector name: X60 Connector type: 38-Pin micro direct connector (optional flat ribbon cable available) Pin No.
7.9 JTAG Interface For connecting a debugger or ICE. Connector name: X61 Connector type: 2x10-pin male connector Pin No. Signal Name Function 1 VTREF 3.3 V reference voltage 2 VSUPPLY 3.
7.11 CPLD Programming Interface The two PLDs on the EB 200 can be parameterized with a programming adapter. The two PLDs are connected in a daisy chain pattern.
Table 27: Connector X10 for Boot Settings and Some Configuration Settings 8.2 System/Configuration Connector X11 Connector X11 is used to specify the remaining configuration modes and various system functions on the EB 200 (for a description of system and configuration modes, refer to Section 2.1.2).
9 9.1 Structure of the EB 200 Mechanical Structure The EB 200 is designed as a PC module with a 174 mm short PCI format. The EB 200 has a standard PC slot plate. The board is equipped with 4 holes onto which the supplied spacers are mounted. 9.2 Front and Display Element external power supply 6 - 9V, 1,5A RJ45 jack with LED’s link and activity 2 LED’s for board state signalisation e.g. RUN and SF Figure 6: Front Element of the EB 200 Copyright © Siemens AG 2010. All rights reserved.
The table below presents the display elements and their functions.
10 Miscellaneous 10.
10.2 References: /1/ /2/ /3/ /4/ /5/ /6/ /7/ ERTEC 200 Data Sheet V1.1.1 (ERTEC200_Data Sheet_V111.PDF); ERTEC 200 Manual V1.1.1 (ERTEC200_Manual_V111.PDF); Guideline_DK_ERTEC200_400_PNIO_ECOS_V310.pdf; Technical Reference Manual ARM946E-S REV1 16 February 2001 (DDI 0201A_946ES.PDF); Technical Reference Manual ARM946E-S 16 December 1999 (DDI_ 0165A_9E-S_TRM. PDF); Embedded Trace Macrocell Architecture Specification (ETM_Spec.PDF); Multi-ICE System Design Consideration Applic.
