Technical data

Segment Contents Größe Adressbereich Beschreibung

5 ARM-ICU 256 MB

5000_0000-

5FFF_FFFF

ARM – Interrupt-Controller

128 Byte physical

Note2

6 Not used 256 MB

6000_0000-

6FFF_FFFF

7 EMIF-Register 256 MB

7000_0000-

7FFF_FFFF

Steuer-Register for external Memory-Interface

64 Byte physical

Note2

8 DMA-Register 256 MB

8000_0000-

FFFF_FFFF

DMA-Controller

16 Byte physikalisch

Note2

9 - 15 Not used 1,75 GB

9000_0000-

FFFF_FFFF

Table 34: Detailed Description of Memory Segments

Note:

1. Access to IRT registers and KRAM should only occur in the address areas indicated above (first 2 Mbytes). An access to areas

within the 2 Mbytes that are not occupied by the IRT registers and KRAM result in undefined access (acknowledgement timeout). The

read or written data are not valid. While the 2-Mbyte areas are mirrored within the 8-Mbyte physical address area, different access types

are used:

¾ 2-4-Mbyte area for unaligned consistent 16-bit accesses to IRT

¾ 4-6-Mbyte area for unaligned consistent 32-bit accesses to IRT

¾ 6-8 Mbytes is not supported (supplies undefined values)

The 8-Mbyte address area is mirrored 32 times within the 256 Mbytes.

2. Memory areas are mirrored according to the following formula:

Memory size

N = --------------------------------------------

Physical memory size

Physical memory size is limited to values of 2

(2, 4, 8, ... 128, 256 etc.)

Example: The physical memory size of the watchdog is 28 bytes. However, 32 bytes are taken for calculating the number of mirrorings

N. In this case, the number of mirrorings N = 8. Access to the 4 unused bytes does not result in an acknowledgement timeout, but the

read or written values are undefined.

Technical data subject to change Version 1.1.0