Technical data

Contents
1 Introduction ............................................................................................................................9
1.1 Applications of the ERTEC 200.............................................................................................................. 9
1.2 Features of the ERTEC 200................................................................................................................... 9
1.3 Structure of the ERTEC 200................................................................................................................... 10
1.4 ERTEC 200 Package ............................................................................................................................. 11
1.5 Signal Function Description.................................................................................................................... 12
1.5.1 GPIO 0 to 31 and Alternative Functions......................................................................................... 12
1.5.2 JTAG and Debug ........................................................................................................................... 13
1.5.3 Trace Port...................................................................................................................................... 13
1.5.4 Clock and Reset ............................................................................................................................ 14
1.5.5 Test Pins........................................................................................................................................ 14
1.5.6 EMIF (External Memory Interface)................................................................................................. 14
1.5.7 LBU, MII Interface or ETM Trace Interface .................................................................................... 16
1.5.8 Ethernet PHY1 and PHY2.............................................................................................................. 18
1.5.9 Power Supply................................................................................................................................. 19
2 ARM946E-S Processor ..........................................................................................................21
2.1 Structure of ARM946E-S........................................................................................................................ 21
2.2 Description of ARM946E-S .................................................................................................................... 22
2.3 Operating Frequency of ARM946E-S..................................................................................................... 22
2.4 Cache Structure of ARM946E-S............................................................................................................. 22
2.5 Tightly Coupled Memory (TCM) ............................................................................................................. 22
2.6 Memory Protection Unit (MPU) .............................................................................................................. 23
2.7 Bus Interface of ARM946E-S ................................................................................................................. 23
2.8 ARM946E-S Embedded Trace Macrocell (ETM9).................................................................................. 23
2.9 ARM Interrupt Controller (ICU)............................................................................................................... 23
2.9.1 Prioritization of Interrupts............................................................................................................... 24
2.9.2 Trigger Modes................................................................................................................................ 24
2.9.3 Masking the Interrupt Inputs .......................................................................................................... 24
2.9.4 Software Interrupts for IRQ............................................................................................................ 24
2.9.5 Nested Interrupt Structure.............................................................................................................. 24
2.9.6 EOI End-Of-Interrupt...................................................................................................................... 24
2.9.7 IRQ Interrupt Sources.................................................................................................................... 25
2.9.8 FIQ Interrupt Sources .................................................................................................................... 25
2.9.9 IRQ Interrupts as FIQ Interrupt Sources ........................................................................................ 26
2.9.10 Interrupt Control Register............................................................................................................... 26
2.9.11 ICU Register Description ............................................................................................................... 27
2.10 ARM946E-S Register............................................................................................................................. 31
3 Bus System of the ERTEC 200..............................................................................................32
3.1 “Multilayer AHB” Communication Bus .................................................................................................... 32
3.1.1 AHB Arbiter.................................................................................................................................... 32
3.1.2 AHB Master-Slave Coupling .......................................................................................................... 32
3.2 APB I/O Bus........................................................................................................................................... 32
4 I/O on APB bus .......................................................................................................................33
4.1 BOOT ROM............................................................................................................................................ 33
4.1.1 Booting from External ROM........................................................................................................... 34
4.1.2 Booting via SPI .............................................................................................................................. 34
4.1.3 Booting via UART .......................................................................................................................... 34
4.1.4 Booting via LBU ............................................................................................................................. 34
4.1.5 Memory Swapping......................................................................................................................... 34
4.2 General Purpose I/O (GPIO).................................................................................................................. 35
4.2.1 Address Assignment of GPIO Registers........................................................................................ 36
4.2.2 GPIO Register Description............................................................................................................. 36
4.3 Timer 0/1/2 ............................................................................................................................................. 38
4.3.1 Timer 0 and Timer 1....................................................................................................................... 38
4.3.1.1 Timer 0/1 Interrupts............................................................................................................... 39
4.3.1.2 Timer 0/1 Prescaler............................................................................................................... 39
4.3.1.3 Cascading of Timers 0/1....................................................................................................... 39
4.3.2 Timer 2........................................................................................................................................... 39
4.3.3 Address Assignment of Timer Registers........................................................................................ 40
4.3.4 Timer Register Description ............................................................................................................ 40
4.4 F-Timer Function.................................................................................................................................... 43
4.4.1 Address Assignment of F-Timer Registers .................................................................................... 44
Copyright © Siemens AG 2007. All rights reserved. Page 5 ERTEC 200 Manual
Technical data subject to change Version 1.1.0