User`s manual

Interrupt System
C501
Semiconductor Group 7-1
7 Interrupt System
The C501 provides 6 interrupt sources with two priority levels. Four interrupts can be generated by
the on-chip peripherals (timer 0, timer 1, timer 2 and serial interface), and two interrupts may be
triggered externally (P3.2/INT0
and P3.3/INT1).
This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special
function registers. Figure 7-25 gives a general overview of the interrupt sources and illustrate the
request and the control flags which are described in the next sections.
Figure 7-25
Interrupt Structure
Timer 2 Overflow
Timer 1 Overflow
MCS01783
TF0
ET0
P1.1/
T2EX
P3.2/
INT0
EA
High Priority
Timer 0 Overflow
TCON.5
PT0
Low Priority
PT1
TCON.7
ET1
TF1
IE.1 IP.1
IP.3
T2CON.3
TF2
EXEN2
T2CON.7
PT2
1
EXF2
TI
1
PS
SCON.0
ES
RI
IE.5 IP.5
IP.4IE.4
IE0
EX0
TCON.1
PX0
ET2
IE.3
IT0
IT1
PX1
TCON.3
EX1
IE1
IE.0 IP.0
INT1
P3.3/
IE.7
TCON.0
TCON.2
SCON.1
T2CON.6
TCON.0
IE.2 IP.2
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