Specifications

AC65/AC75 Hardware Interface Description

3.15 Audio Interfaces

AC65_AC75_HD_v01.002 Page 63 of 117 2006-10-30

Confidential / Released

In all configurations the PCM interface has the following common features:

• 16 Bit linear

• 8kHz sample rate

• the most significant bit MSB is transferred first

• 125µs frame duration

• common frame sync signal for transmit and receive

Table 16 shows the assignment of the DAI0...6 pins to the PCM interface signals. To avoid hardware conflicts

different pins are used as inputs and outputs for frame sync and clock signals in master or slave operation. The

table shows also which pin is used for master or slave. The data pins (TXDAI and RXDAI) however are used in

both modes. Unused inputs have to be tied to GND, unused outputs must be left open.

3.15.4.1 Master Mode

To clock input and output PCM samples the PCM interface delivers a bit clock (BITCLK) which is synchronous

to the GSM system clock. The frequency of the bit clock is 256kHz or 512kHz. Any edge of this clock deviates

less than ±100ns (Jitter) from an ideal 256-kHz clock respectively deviates less than ±320ns from an ideal 512-

kHz clock.

The frame sync signal (FS) has a frequency of 8kHz and is high for one BITCLK period before the data trans-

mission starts if short frame is configured. If long frame is selected the frame sync signal (FS) is high during the

whole transfer of the 16 data bits. Each frame has a duration of 125µs and contains 32 respective 64 clock

cycles.

Figure 28: Master PCM interface Application

Table 16: Overview of DAI pin functions

Signal name on

B2B connector

Function for PCM Interface Input/Output

DAI0 TXDAI Master/Slave O

DAI1 RXDAI Master/Slave I

DAI2 FS (Frame sync) Master O

DAI3 BITCLK Master O

DAI4 FSIN Slave I

DAI5 BCLKIN Slave I

DAI6 nc I