Specifications

7SR242 Duobias Description Of Operation

List of Figures

Figure 1-1 Functional Diagram: 7SR242_-2_A_1-0AA0 Relay............................................................9

Figure 1-2 Functional Diagram: 7SR242_-2_A_1-0BA0 Relay..............................................................10

Figure 1-3 Functional Diagram: 7SR242_-2_A_1-0CA0 Relay .............................................................11

Figure 1-4 Connection Diagram: 7SR242 Relay................................................................................12

Figure 2-1 7SR24 with 3 + 16 LEDs in E8 Case................................................................................14

Figure 2-2 Binary Input Logic .............................................................................................................17

Figure 2-3 Binary Output Logic ..........................................................................................................19

Figure 3-1 Biased Differential Characteristic..........................................................................................21

Figure 3-2 Functional Diagram for Biased Current Differential Protection.............................................22

Figure 3-3 Differential Highset Characteristic ........................................................................................23

Figure 3-4 Logic Diagram: High Set Current Differential Protection ......................................................24

Figure 3-5 Logic Diagram: Instantaneous Over-current Element .......................................................25

Figure 3-6 Logic Diagram: Time Delayed Overcurrent Element.........................................................26

Figure 3-7 Logic Diagram: Instantaneous Derived Earth Fault Element ............................................27

Figure 3-8 Logic Diagram: Derived Time Delayed Earth Fault Protection..........................................28

Figure 3-9 Logic Diagram: Measured Instantaneous Earth-fault Element..........................................29

Figure 3-10 Logic Diagram: Time Delayed Measured Earth Fault Element (51G)...............................30

Figure 3-11 Logic Diagram: High Impedance REF (64H)......................................................................31

Figure 3-12 Logic Diagram: Open Circuit Function (46BC) ..................................................................32

Figure 3-13 Logic Diagram: Negative Phase Sequence Overcurrent (46NPS)....................................33

Figure 3-14 Logic Diagram: Undercurrent Detector (37, 37G)..............................................................34

Figure 3-15 Logic Diagram: Thermal Overload Protection (49)............................................................36

Figure 3-16 Inverse Over-fluxing Characteristic (24IT)..........................................................................37

Figure 3-17 Logic Diagram: Overfluxing Elements (24).........................................................................38

Figure 3-18 Logic Diagram: Under/Over Voltage Elements (27/59) .....................................................39

Figure 3-19 Logic Diagram: Neutral Overvoltage Element ...................................................................40

Figure 3-20 Logic Diagram: Under/Over Frequency Detector (81).......................................................41

Figure 4-1 Sequence Diagram showing PU/DO Timers in Quick Logic (Counter Reset

Mode Off) ...........................................................................................................................43

Figure 5-1 Logic Diagram: Circuit Breaker Fail Protection (50BF).........................................................44

Figure 5-2 Logic Diagram: Trip Circuit Supervision Feature (74TCS) ................................................45

Figure 5-3 Logic Diagram: Close Circuit Supervision Feature (74CCS).............................................45

Figure 5-4 Logic Diagram: Inrush Detector Feature (81HBL2)...........................................................46

Figure 5-5 Logic Diagram: Overfluxing Detector Feature (81HBL5)...................................................46