User Manual

Logical I/O blocks
Addressing the I/O blocks
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CM110664en_07 267 | 351
Solution 2
The multiple use function can be implemented with a BACnet reference to the first analog input block
(Partial plant 1). In other words, the first block will receive the island bus address at the [IOAddr] pin. The
second analog input block (Partial plant 2) references the first AI (B=…) via the technical designation.
Addressing multistate I/Os
Multistate input
The multistate value is made up of several separate binary measured values.
Addressing is via the input/output address [IOAddr]. In both the modular and the compact series, the
logical and physical I/O must be "located" in the same automation station, but they do not need to be
contiguous (e.g., C=5.1;5.3;5.5;5.6(Q250) is valid). The addressing cannot extend across automation
stations. The addresses must be on the same module for TX-I/O.
For information about adressing multistate I/Os with PTM, see
Addressing Multistate I/Os with PTM .
Simple mapping
Syntax: T=Module.I/O point;Module.I/O point;Module.I/O point;Module.I/O point
Examples:
● T=1.1
● T=1.1;1.2
● T=1.1;1.2;1.3
● T=1.1;1.2;1.3;1.4
● T=10.3
Up to four binary status values (e.g., Off/St1/St2/St3/St4) can be registered. The signals to be registered,
which are addressed via Module.Channel, must always be of the same hardware signal type. With the
simple mapping procedure, to enable the multistate input to interpret the current binary signals correctly,
only one binary signal may be present at any one time. If several binary signals are present at once, this is
displayed as an error at the [Rlb] pin.
The examples below show a possible application for multistate input blocks in conjunction with the
physical I/O modules. The example on the left of the diagram is a multiple I/O module, while the one on the
right shows the mapping of several individual I/O modules in one multistate input block.
Multistate output
I/O module
Block
1
0
6
6
4
-
2
4
z
0
3
e
n
Analog input
T