Specifications
~
_____
I_ND_E_X
________________________________________________________________
_
MFM
10416 BYTES
----------------
.....
REPEAT FOR EACH RECORD
---------+t
G.A
I·~~~~
I
~:~
I
~M
I
G1
~Nel
~ci'~M
I AM
1,0
I
eRe
I
G'
I
DATA
16~~AI
AM I DATA I CRC I WG I G3
SYNC
AM
OFF
G4B
4E
00
m FC
3
4E
00 m
FE
[II
8]
4E
00 III m 40
8]
4E
4E 4E
DATA
80
12
80
12
3
80
12
3
50
50
50
12
12
12
4
3
4
3 4
22
12
1024 2
22
12 512 2
22
12
3
256
115
83
53
654
400
598
BYTES/8 REC.
BYTES/15 REC.
BYTES/26 REC.
UPDATE
WRITE
OJ
3 BYTES C2 WITH UNIQUE CLOCK PATTERN 14
ill
3 BYTES
A1
WITH UNIQUE CLOCK PATTERN
OA
m TRACK NUMBER, HEAD NUMBER, SECTOR, RECORD LENGTH
m GENERATED
BY
CRC GENERATOR WHICH SHOULD
BE
EQUIVALENT TO CCITT
VH1
rn
1 BYTE OF FB
OR
F8
50574·32
Gap
1-
FIGURE 6·7.
MFM
TRACK FORMAT COMPARISON
G4A
is
from the physical index address mark sync and allows for physical index variation,
speed
variation,
and
interchange between storage devices.
Sync
is
a fixed number of bytes for separator synchronization prior to the address mark.
It
in-
cludes a minimum of two bytes plus worst case separator sync
up
requirements.
Index
Pre Address
Mark
(MFM)
is
three bytes of
C2
with unique clock bits not written
per
the
encode
rules.
See
figure 6-8.
Index Address
Mark
(FM)
is
a unique byte to identify
the
index field
and
is
not written
per
the
encode
rules.
See
figure 6-9.
Index Address
Mark
(MFM)
is
one
byte of FC
and
is
written
per
the
encode
rules.
See
figure
6-10.
Gl
is
from index address mark to 10 field address mark sync.
10
Field
- Sync
is
a fixed
number
of bytes for separator synchronization prior to
the
address mark. It in-
cludes a minimum of two bytes plus worst case separator sync
up
requirements.
Gap
2-
10
Pre Address
Mark
(MFM)
is
three bytes of A 1 with unique clock bits
not
written
per
the
encode
rules.
See
figure 6-8.
10
Address
Mark
(FM) is a unique byte to identify
the
10
field
and
is
not written
per
the
en-
code
rules.
See
figure 6-11.
10
Address
Mark
(MFM)
is
one
byte of
FE
and
it
is
written
per
the
encode
rules.
See
figure
6-12.
10
is
a four byte address containing track number,
head
number,
record number,
and
record
length.
CRC
is
two bytes for cyclic
redundancy
check.
Gap
2
is
from IDCRC to
data
address mark sync
and
allows for
speed
variation, oscillator
variation,
and
erase
core clearance of IDCRC bytes prior to write gate turn
on
for
an
update
write.
6-5