Specifications
If
a single sided diskette
is
installed, READY
will
be active (logical zero) when SIDE a
is
selected, but false (logical-
one) when
SIDE 1
is
selected. Conversely, if a two-sided diskette
is
installed, READY
will
be active when either
side of the diskette
is
selected.
For additional methods of using the READY line, refer to paragraph 7.11.
NOTE
READ DATA,
SEP
DATA,
and
SEP
CLOCK are only present when DRIVE SELECT
and
TRUE
READY are active
(low)
and
WRITE GATE
is
inactive (high).
2.2.17
Read Data
This interface line provides the "raw data" (clock
and
data together) as detected by the drive electronics. Normally,
this signal
is
a logical
one
level
and
becomes a logical zero level for the active state.
See
figure
1-
6 for
the
timing
and
bit shift tolerance within normal media variations.
2.2.18
Sep
Data
This interface line furnishes the data bits as separated from the "raw data"
by
use of the internal
FM
data separator.
Normally, this signal
is
a logical
one
level
and
becomes a logical zero level for the active state.
See
figure 1-6 for the
timing.
2.2.19
Sep
Clock
This interface line furnishes the clock bits as separated from the "raw data"
by
use of the internal
FM
data separator.
Normally, this signal
is
a logical
one
level
and
becomes a logical zero level for the active state.
See
figure 1-6 for the
timing.
2.2.20
Write
Protect
This interface signal
is
prOVided
by
the drive to give the user an indication when a write protected diskette is install-
ed. This signal
is
a logical zero level when
it
is
protected. Under normal operation, the drive
will
inhibit writing with
a protected diskette installed
in
addition to notifying the interface.
For other methods of using write protect. refer to paragraph
7.13.
2.2.21
True Ready
This
output
(pin
8)
signals that the drive
is
ready to handle data. The line
will
come
true (active low) when the
diskette
is
up to speed,
all
seek functions have been completed, and the READY line
is
active (refer to paragraph
2.2.16).
It
is
recommended
that this signal be used
in
place of motor start
and
seek complete timers.
2.2.22
Disk
Change (Optional Output)
Reference paragraph 7.4.
2.2.23
Two
Sided
(Optional Output)
Reference paragraph 7.3.
2.2.24
Alternate
I/O
Pins
These interface lines (pins 4
and
6)
have been provided for use with customer installable options. Refer to Section
VII
for methods of use.
2.3
POWER INTERFACE
The
SA81a
and
SA86a require only dc power for operation. DC
power
to the drive
is
provided via
P2/
J210cated
on
the
component
side of the PCB
near
the stepper motor. The two dc voltages, their specifications,
and
their
P2/
J2
pin designators are outlined
in
table 2-1. The specifications outlined
on
current requirements are for
one
drive. For multiple drive systems, the current requirements
are
a multiple of the maximum current times the
number of drives
in
the system.
See
figure 2-5 for the dc
power
requirements during various operations.
2-6