Specifications
1.4.10
Sequence
Of
Events
The
timing diagram shown
in
figure 1-9 illustrates the necessary
sequence
of events with associated timing restric-
tions for
proper
operation.
DC POWER
VALID CONTROL
~90ms
MIN
AND
OUTPUT SIGNALS
90
I
DRIVE SELECT
SIDE SELECT
(SA860 ON
L
Y)
DIRECTION
SELECT
STEP
TRUE READY
WRITE GATE
WRITE DATA
VALID READ
DATA
SIGNAL
ms
MIN
----.
I I
I
I
I
ss
~500mSMAX
*r--,
*,--'
, ,
,I
1_
100
;.--
~
I
~\~
___
...L.'
~I
---\:~\~-------
r-
MAX
SS
~S
I
1
1 s I
{m~t
1
S~
_II
T --
.....
l---\S\oS---------
M)N
~
r-
HMIN~
Mf~
....
~
1 /ls MIN
~S
90
m~
I I
Ln
1 /ls I
tn.J~----\'t-----
MIN
..
~
~
~NOTE2~16ms
NOTE
2~
-.J
t....MIN
16
ms-.i
l.-
II
~6
m~1
MI~r------J
--·L
~
----"S'"S---
II~IN
r-16
ms
I
I I
SS
I MIN I
...
I..
I I 100
••
MIN
;;
~
J.oI-f----~----''---
NOTE 1
~
r-
4 /ls M IN I
~
L16
~.
lnf1ru~I--
1-
MIN
~
r-
50
/ls MIN
---:"'-~-NO-TE
l=tnfWJ
\~
NOTE
1:
165
ms
minimum
delay
must
be
introduced
after
DRIVE SELECT
to
allow
time
for
the
dc
motor
to
reach 360 rpm
or
the
optional
TRUE READY line
must
be
monitored.
NOTE
2:
If
performing
standard seeks, the
minimum
frequency is 3
ms
between steps. If
utilizing
the drive in
the
buffered
seek mode
of
operation the frequency shall be
15
p..s
to
2.9
ms
between pulses.
*
After
the last
step
pulse has been issued, the drive may be deselected. The drive ignores any change
to
the
DIRECTION SELECT line when no
further
step
pulses
are received.
This
frees the
controller
to
issue
instructions
to
other
drives
while
the
first
drive
completes
the
step
commands
stored in the
buffer.
39216·08·A
FIGURE 1·9. SA810/860 GENERAL CONTROL AND DATA TIMING REQUIREMENTS
1-10