Specifications

3 CPU Core Information 5

CW6631B Bluetooth Audio Player Microcontroller Version 1.0.0

3 CPU Core Information

3.1 Architecture

The AXC51-CORE of CW6631B is fully compatible with the MCS-51

instruction set.

The AXC51-CORE employs a pipelined architecture that greatly increases its instruction throughput over the

standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock

cycles to execute, and usually have a maximum system clock of 12MHz. By contrast, the AXC51-CORE executes

most of its instructions in 1 system clock cycle. With system clock running at 48 MHz, it has a peak throughput of 48

MIPS running in on-chip SRAM area.

3.2 Instruction Set

The instruction set of the AXC51-CORE is fully compatible with the standard MCS-51

instruction set; standard

8051 development tools can be used to develop software for the AXC51-CORE. All instructions of AXC51-CORE

are the binary and functional equivalent of their MCS-51

counterparts, including op-codes, addressing modes and

effect on PSW flags. However, instruction timing is different than that of the standard 8051. Table 3-1 shows

AXC51-CORE Instruction Set Summary

Table 3-1 AXC51-CORE Instruction Set Summary

Number of Bytes Mnemonic Operands Clock Cycles (running in IRAM)

1 NOP 1

2 AJMP code addr 3

3 LJMP code addr 3

1 RR A 1

1 INC A 1

1 INC data addr 1

1 INC @Ri 1

1 INC Rn 1

3 JBC bit addr, code addr 1 or 3

2 ACALL code addr 3

3 LCALL code addr 3

1 RRC A 1

1 DEC A 1

2 DEC data addr 1

1 DEC @Ri 1

1 DEC Rn 1

3 JB bit addr, code addr 1 or 3

1 RET 4

1 RL A 1

2 ADD A, #data 1