Data Sheet

AMD Confidential—Advance Information
AMD RZ608™ Data Sheet
56932 Rev. 0.50 August 2020
18
Electrical Characteristics
Chapter 4
4.2 Global Reset
The AMD RZ608 supports two global resets as follows:
• Cold reset by AVDD33_BUCK, AVDD33_MISC, PMU_EN ⸺ Whole Chip reset.
• MCU WDT (watch-dog-timer) reset ⸺ Reset digital circuit, except strapping, PMU, and
XTAL controller.
Figure 3.. Global Reset
4.3 PCIE Interface
The AMD RZ608 supports the following:
• PCI Express End Point, which is fully compliant with the PCI Express Base Specification
Revision 2.1. It supports PCI Express Gen1 (2.5Gbps) and PCIE Express Gen2 (5.0Gbps)
differential bus speeds.
• PCI Express low power operations such as ASPM L1.0, ASPM L1.CLK_PM, ASPM L1.SS
(L1.1 and L1.2), and PCI PM L2 state. It also supports WAKE_N for the device wakeup host
scenario, as well as a remote wake-up signaling.
The PCI Express interface is only used for Wi-Fi operations. The DMA ring and the data structure
are controlled by the descriptor based PDMA engine over PCI Express interface.
4.4 USB Interface
The AMD RZ608 supports the USB device port, which is fully compliant with the Universal
Serial Bus Specification, Revision v2.0 (USB v2.0 specification). It supports high-speed mode,
suspend/resume signaling, as well as remote wake-up signaling.