User's Manual

KF-XXXX-X-XXX-版本
(referenced to CLK)
Input Hold Time tIH 5 - - ns
Output Delay time-Data
Transfer Mode
tODLY - - 14 ns
Outputs: CMD, DAT
(referenced to CLK)
Output Delay time-Identification
Mode
tODLY - - 50 ns
Remark: Timing is based on CL < 40pF load on CMD and Data.
1.7.3.3.2 High Speed Mode
Figure 6 WLAN SDIO Timing, High Speed Mode
Table 10 WLAN SDIO Timing, High Speed Mode
Parameter Symbol Min Typ Max Unit
Frequency-Data Transfer Mode fPP 0 - 50 MHz
Frequency-Identification Mode fOD 0 - 400- KHz
Clock Low Time tWL 7 - - ns
Clock High Time tWH 7 - - ns
Clock Rise Time tTLH - - 3 ns
Clock CLK (All
values are referred
to min. VIH and max.
VIL)
Min (Vih) = 0.7*VIN
and max (Vil) =
0.2*VIN
Clock Falling Time tTHL - - 3 ns
Input Setup Time tISU 6 - - ns
Inputs: CMD, DAT
(referenced to CLK)
Input Hold Time tIH 2 - - ns
Outputs: CMD, DAT Output Delay time-Data tODLY - - 14 ns