User's Manual

KF-XXXX-X-XXX-版本
V OL output logic level low (100μA load)
- - 0.4 V
Output Voltage
V
OH output logic level high (-100μA load)
2.4 - - V
I IL input logic level low - 0.3 - uA
Input Current:
I
IH input logic level high - 0.3 - uA
I OL output logic level low (V OL =0.4V) - - 3.0 mA
Output Current
I
OH output logic level high (V OH =2.9V) - - 3.0 mA
Input Capacitance :C IN - - 5 pF
1.7.3.3 WLAN SDIO Timing
1.7.3.3.1 Default Mode
Figure 5 WLAN SDIO Timing, Default Mode
Table 9 WLAN SDIO Timing, Default Mode
Parameter Symbol Min Typ Max Unit
Frequency-Data Transfer Mode fPP 0 - 25 MHz
Frequency-Identification Mode fOD 0 - 400- KHz
Clock Low Time tWL 10 - - ns
Clock High Time tWH 10 - - ns
Clock Rise Time tTLH - - 10 ns
Clock CLK (All
values are referred
to min. VIH and max.
VIL)
Min (Vih) = 0.7*VIN
and max (Vil) =
0.2*VIN
Clock Falling Time tTHL - - 10 ns
Inputs: CMD, DAT Input Setup Time tISU 5 - - ns