KF-XXXX-X-XXX-版本 No. Pin name Type System Description 1 SD_CLK I WLAN 2 VIN I Common 3 SD_CMD I/O WLAN 4 GND I Common 5 SD_D0 I/O WLAN SDIO Data Line 0. 6 /WL_RESET I WLAN Low asserting reset for WLAN core. 7 SD_D1 I/O WLAN SDIO Data Line 1. 8 SLEEP_CLK I Common 9 SD_D2 I/O WLAN SDIO Clock. 3.3V Power supply input. SDIO Command Line. Ground. Low Power Clock input (32.768kHz). SDIO Data Line 2.
KF-XXXX-X-XXX-版本 SW1=0,SW2=1,Select antenna 2 26 BT_UART_CTS I BT Bluetooth UART clear to send. Active-low clear-to-send signal for the HCI UART interface. Antenna select. 27 SW2 I Common SW1 and SW2 are floating, Select antenna 1 SW1=1,SW2=0,Select antenna 1 SW1=0,SW2=1,Select antenna 2 28 TYPE O Common Cyberlink type Detect. PIN tie to 3.3V. GND I Common Ground. 30 VIN I Common 3.3V Power Input 31 /BT_RESET I BT Low asserting reset for Bluetooth core.
KF-XXXX-X-XXX-版本 51 WL_RXD 52 NC I WLAN RX pin of debug UART No use 1.7.2 Power On Sequence 1.7.2.1 Power On Sequence 1 VIN Figure 2 Power On Sequence 1 1.7.2.2 Power On Sequence 2 VIN Figure 3 Power On Sequence 2 1.7.2.
KF-XXXX-X-XXX-版本 VIN VIN Figure 4 Power On Sequence 3 1.7.3 Interface 1.7.3.1 External Clock Reference (SLEEP_CLK) Table 7 External Clock Reference Parameter Description Nominal input frequency Remarks 32.
KF-XXXX-X-XXX-版本 - - 0.4 V 2.4 - - V IIL input logic level low - 0.3 - uA IIH input logic level high - 0.3 - uA IOL output logic level low (VOL =0.4V) - - 3.0 mA IOH output logic level high (VOH =2.9V) - - 3.0 mA - - 5 pF VOL output logic level low (100μA load) Output Voltage VOH output logic level high (-100μA load) Input Current: Output Current Input Capacitance :CIN 1.7.3.3 WLAN SDIO Timing 1.7.3.3.
KF-XXXX-X-XXX-版本 (referenced to CLK) Input Hold Time Outputs: CMD, DAT (referenced to CLK) Output Delay Transfer Mode tIH 5 - - ns time-Data tODLY - - 14 ns Output Delay time-Identification Mode tODLY - - 50 ns Remark: Timing is based on CL < 40pF load on CMD and Data. 1.7.3.3.2 High Speed Mode Figure 6 WLAN SDIO Timing, High Speed Mode Table 10 WLAN SDIO Timing, High Speed Mode Parameter Symbol Min Typ Max Unit Clock CLK (All values are referred to min. VIH and max.
KF-XXXX-X-XXX-版本 (referenced to CLK) Transfer Mode Output Hold time Total System (each line) Capacitance tOH - - 50 ns CL - - 40 pF Remark: Timing is based on CL < 40pF load on CMD and Data. 1.7.4 Mechanical This device complies with Industry Canada licence-exempt RSS standard(s).
KF-XXXX-X-XXX-版本 Appendix A FCC A.1 FCC statement in User's Manual (for class B) "Federal Communications Commission (FCC) Statement This Equipment has been tested and found to comply with the limits for a class B digital device, pursuant to Part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
