User's Manual

16
6) Receiving CTCSS/CDCSS signal
300Hz-and-higher audio frequency of the signal output from IC3 is filtered by low-pass
filter IC2-B, C，D. The resulting signal TI enters the microprocessor IC8. IC8 determines
whether the CTCSS/CDCSS matches the pre-set value, and controls the RX-MUTE, APA
and the speaker output sounds according to the squelch result.
3. PLL Synthesizer
PLL circuit generates the first local oscillator signal for reception and the RF
signal for transmission.
1) PLL circuit
The step frequency of PLL circuit is 5 KHz or 6.25 KHz. A 21.25MHz reference oscillator
signal is divided at IC1 by a mixed counter to create a 5 KHz or 6.25 KHz reference
frequency. Output signal from VCO enters the 16 pin of IC1 and is divided at IC1 by a
dual-module programmable counter. The divided signal is compared in the phase
comparator IC1 with a 5 KHz or 6.25 KHz reference signal. The signal from phase
comparator is filtered through a low-pass filter and generates a VCO voltage adding to
varicap diodes D10 to control the oscillator frequency. (See Figure 4)
Fig.4 PLL Circuit
2) VCO
Q4 composes Colpitts oscillator circuit together with the outside circuit. The oscillator
frequency is controlled by PLL. In receive mode, the oscillator frequency is the first local
oscillator frequency for reception. In transmit mode, the oscillator frequency is the RF
frequency for transmission.