Data Sheet

FSC‐BT630Datasheet
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corruptioniftwoormoremastersattempttocontrolthebussimultaneously.
DataistransferredbetweenaMasterandaSlavesynchronouslytoSCLontheSDAlineonabyte‐by‐bytebasis.Each
data byte is 8‐bit long. There is one SCL clock pulse for each data bit
 with the MSB being transmitted first. An
acknowledgebitfollowseachtransferredbyte.EachbitissampledduringthehighperiodofSCL;therefore,theSDA
line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A
transition
ontheSDAlinewhileSCLishighisinterpretedasacommand(STARTorSTOP).Pleaserefertothefollowing
figureformoredetailsaboutI2CBusTiming.
Thedeviceon‐chipI2ClogicprovidestheserialinterfacethatmeetstheI2Cbusstandardmodespecification.TheI2C
porthandlesbyte transfersautonomously.The I2CH/Winterfacestothe I2Cbusvia twopins:SDA andSCL.Pull up
resistorisneededforI2Coperationastheseareopendrainpins.WhentheI/OpinsareusedasI2Cport,usermustset
thepinsfunctiontoI2Cinadvance.
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TheI2CmasteriscompatiblewithI2Coperatingat100kHzand400kHz.
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 4.9Pulsewidthmodulation(PWM)
ThePWMmoduleenablesthegenerationofpulsewidthmodulatedsignalsonGPIO.Themodule implementsanupor
up‐and‐downcounterwithfourPWMchannelsthatdriveassignedGPIOs.
Three PWM modules can provide up to 12 PWM  channels with individual frequency control in groups of up to four
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channels. Furthermore, a built‐in decoder and EasyDMA capabilities make it possible to manipulate the PWM duty
cycles without CPU intervention. Arbitrary duty‐cycle sequences are read from Data RAM and can be chained to
implementping‐pongbufferingorrepeatedintocomplexloops.
Listedherearethemainfeatures
ofonePWMmodule:
FixedPWMbasefrequencywithprogrammableclockdivider
UptofourPWMchannelswithindividualpolarityandduty‐cyclevalues
Edgeorcenter‐alignedpulsesacrossPWMchannels
Multipleduty‐cyclearrays(sequences)definedinDataRAM
Autonomousandglitch‐freeupdateofdutycyclevaluesdirectlyfrommemorythroughEasyDMA
Changeofpolarity,duty‐cycle,andbasefrequencypossiblyoneveryPWMperiod
DataRAMsequencescanberepeatedorconnectedintoloops
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4.10Pulsedensitymodulationinterface(PDM)
The pulse density modulation (PDM) module enables input of pulse density modulated signals from external audio
frontends,forexample,digitalmicrophones.ThePDMmodulegeneratesthePDMclockandsupportssingle‐channelor
dual‐channel(LeftandRight)datainput.DataistransferreddirectlytoRAMbuffersusingEasyDMA.
Listedhere
arethemainfeaturesforPDM:
UptotwoPDMmicrophonesconfiguredasaLeft/Rightpairusingthesamedatainput
16kHzoutputsamplerate,16‐bitsamples
EasyDMAsupportforsamplebuffering