Data Sheet

FSC‐BT630Datasheet
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 ShenzhenFeasycomTechnologyCo.,Ltdwww.feasycom.com
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•Onechannelpersingle‐endedinputandtwochannelsperdifferentialinput
•Scanmodecanbeconfiguredwithbothsingle‐endedchannelsanddifferentialchannels.
Fullscaleinputrange(0toVDD)
SamplingtriggeredviaataskfromsoftwareoraPPIchannelforfullflexibilityonsamplefrequencysourcefromlow
power32.768kHzRTCormoreaccurate1/16MHzTimers
One‐shotconversionmodetosampleasinglechannel
Scanmodetosampleaseriesofchannelsinsequence.Sampledelaybetweenchannelsistack+tconvwhichmay
varybetweenchannelsaccordingtouserconfigurationoftack.
SupportfordirectsampletransfertoRAMusingEasyDMA
Interruptsonsinglesampleandfullbufferevents
Samplesstoredas16‐bit2’scomplementvaluesfordifferentialandsingle‐endedsampling
Continuoussamplingwithouttheneedofanexternaltimer
Internalresistorstring
Limitcheckingonthefly
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 4.4GeneralPurposeDigitalIO
There are 13 general purpose digital IOs defined in the module. All these GPIOs can be configured by software to
realizevariousfunctions,suchasbuttoncontrols,LEDdrivesorinterruptsignalstohostcontroller,etc.Donotconnect
themifnotuse.
TheI/OtypeofeachI/OpinscanbeconfiguredbysoftwareindividuallyasInputorPush‐pulloutputmode.Afterthe
chip is reset, the I/O mode of all pins is input mode with no pull‐up and pull‐down enable. Each I/O pin has an
individualpull‐upandpull‐downresistorwhichisabout40
kΩforVDDandVss.
Configurableoutputdrivestrength
Internalpull‐upandpull‐downresistors
Wake‐upfromhighorlowleveltriggersonallpins
Triggerinterruptonstatechangesonanypin
AllpinscanbeusedbythePPItask/eventsystem
OneormoreGPIOoutputscanbecontrolledthroughPPIandGPIOTEchannels
Allpinscanbeindividuallymappedtointerfaceblocksforlayoutflexibility
GPIOstatechangescapturedonSENSEsignalcanbestoredbyLATCHregister
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4.5I2SInterfaces
The I2S (Inter‐IC Sound) module, supports the original two‐channel I2S format, and left or right‐aligned formats. It
implementsEasyDMAforsampletransferdirectlytoandfromRAMwithoutCPUintervention.
TheI2Speripheralhasthefollowingmainfeatures:
MasterandSlavemode
Simultaneousbi‐directional(TXandRX)audiostreaming
OriginalI2Sandleft‐orright‐alignedformat