Service manual

6. SSP circuit

1) Block diagram

This is the circuit employed to do the Special Service Preset(SSP).

(Block diagram)

Fig. 6-1

(MPCA6 block diagram)

Fig. 6-2

As the address detection system, the brake address register compari-

son system is employed though the mapping system was employed

in the conventional monitor RAM. The address registerlocated in

MPCA is always compared with the system address bus to monitor

and generate NMI signal at a synchronized timing and togo to NMI

exception process.

In the exception process routine service routine, the entry address is

checked to go to SSP sub routine.

Entry to the break address register (BAR) is performed through ad-

dress FFFF00H or later decoded in MPCA6.

2) SSP register

The break address register (BAR) is accessed through direct address

of FFFF00H~FFFFFFH. Entry number is 32 entry.

Fig. 6-3

CPU MPCA6

A0~23

D0~D7

NMI

SSPRQ

D0~

A23~

BAR 0

BAR N

REGCS

Decode

Comparator

Coincide

SPE

(Enable register)

SSPRQ

(NMI)

Control signal

ROMCS

FFFF00

BAR0

BAR1

BAR2

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