Programming instructions

CMOS
Multisim Component Reference Guide 7-14 ni.com
7.2.24 40194 (4-bit Shift Register)
7.2.25 40195 (4-bit Shift Register)
7.2.26 4020 (14-stage Bin Counter)
7.2.27 4021 (8-bit Static Shift Register)
The 4021 device is an 8-bit static shift register (parallel-to-serial converter) with a
synchronous serial data input (D
S
), a clock input (CP), an asynchronous active HIGH parallel
load input (PL), eight asynchronous parallel data inputs, and buffered parallel outputs from
the last three stages.
The 40194 device is a 4-bit bidirectional shift register with two mode control inputs (S0 and
S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input
(DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input
(MR
), and four buffered parallel outputs (O0 to O3).
The 40195 device is a fully synchronous edge-triggered 4-bit shift register with a clock
input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data
inputs (J, K
), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-
bit positions (O0 to O3), a buffered inverted output from the last bit position (O
3) and an
overriding asynchronous master reset input (MR
).
The 4020 device is a 14-stage binary ripple counter with a clock input (CP
), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs.
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