Programming instructions
CMOS
Multisim Component Reference Guide 7-8 ni.com
Shift register truth table:
7.2.13 40160 (4-bit Dec Counter)
n CP D MR O0 O1 O2 O3
1 ·D10D1XXX
2·D20D2D1XX
3 · D3 0 D3D2D1 X
4 · D4 0 D4D3D2D1
‚ X 0 no change
XX10000
1 = HIGH state (the more positive voltage)
0 = LOW state (the less positive voltage)
X = state is immaterial
· = positive-going transition
‚ = negative-going transition
Dn = either HIGH or LOW
n = number of clock pulse transitions
The 40160 device is a fully synchronous edge-triggered 4-bit decade counter with a clock
input (CP), an overriding asynchronous master reset (MR
), four parallel data inputs (P0 to
P3), three synchronous mode control inputs (parallel enable (PE
), count enable parallel
(CEP) and count enable trickle (CET)), buffered outputs from all four bit positions (O0 to
O3) and a terminal count output (TC).
ComponentRef.book Page 8 Thursday, December 7, 2006 10:12 AM