Programming instructions

TTL
Multisim Component Reference Guide 6-38 ni.com
Shift register truth table:
6.4.68 74xx198 (8-bit Shift Reg (shl/shr ctrl))
This bidirectional register has parallel inputs, parallel outputs, right-shift and left-shift serial
inputs, operating-mode-control inputs, and a direct overriding clear line.
Shift register truth table:
SERIAL PARALLEL OUTPUTS
CLEAR
SHIFT/
LOAD
CLK J K
A B C D QA QB QC QD QD
0 X XXXXXXX00001
1 0 · X X abcda b c d
d
1 1 0 X X XXXXQA0QB0QC0QD0QD0
1 1 · 0 1 XXXXQA0QA0QBnQCnQ
Cn
1 1 · 0 0 XXXX0 QAnQBnQCnQ
Cn
1 1 · 1 1 XXXX1 QAnQBnQCnQ
Cn
1 1 · 1 0 XXXXQ
An QAn QBn QCn QCn
· = transition from low to high
a, b, c, d = the level of steady state input at inputs A, B, C, or D respectively
QA0, QB0, QC0,
QD0
= the level of QA, QB, QC, or QD, respectively, before the indicated steady state
input conditions were established
QAn, QBn, QCn = the level of QA, QB, QC before the most recent negative transition of the clock
MODE SERIAL PARALLEL OUTPUTS
CLEAR
S1 S0 CLK LEFT RIGHT A ... h QA QB ... QG QH
0 XXXX X X 00 0 0
1 X X 0 X X X QA0 QB0 QG0 QH0
1 11· X X a...h ab g h
1 0 1 · X 1 X 1 QAn QFn QGn
1 0 1 · X 0 X 0 QAn QFn QGn
1 10· 1 X X QBnQCnQHn1
1 10· 0 X X QBnQCnQHn1
1 0 0 X X X X QA0 QB0 QG0 QH0
ComponentRef.book Page 38 Thursday, December 7, 2006 10:12 AM