Programming instructions

TTL
Multisim Component Reference Guide 6-28 ni.com
6.4.53 74xx166 (Parallel-load 8-bit Shift Reg)
This shift-register is a parallel-in or serial-in, serial out device. It shifts the data in the
direction of QA toward QH when clocked. It features an active-low clear input. To load the
data at the 8-inputs into the device, apply a low level at the shift/load input.
Shift register truth table:
6.4.54 74xx169 (Sync 4-bit up/down Binary Counter)
This synchronous presettable 4-bit binary counter has an internal carry look-ahead for
cascading in high speed counting applications.
Up/down counter truth table:
INPUTS
INTERNAL
O/P
OUTPUTS
CLR
SHIFT/
LOAD
CLK INH CLK SERIAL
PARALLEL
A through H
QA
QB QH
0X X XX XXXX00 0
1X 0 0 X XXXXQA0QB0QH0
10 0 · X A TO H ab1
11 0 · 1 XXXX1 QAnQGn
11 0 · 0 XXXX0 QAnQGn
1X 1 · X XXXXQA0QB0QH0
· = transition from low to high
a,b,c,d = the level of steady state input at A, B, C, or D respectively
ENP ENT D/U CLK LOAD A B C D QAQBQCQDRCO
00XX0 XXXXABCD1*
001· 1 XXXXCount Down 1*
000· 1 XXXXCount Up 1*
1XXXX XXXXQa0Qb0Qc0Qd01*
X1XXX XXXXQa0Qb0Qc0Qd01*
1* = during the UP count RCO goes LOW at count 15.
during the DOWN count RCO goes LOW at count 0.
ComponentRef.book Page 28 Thursday, December 7, 2006 10:12 AM