System information

Map and Paging Control Register
VSBC-6 Reference Manual Reference – 57
Map and Paging Control Register
MPCR (READ/WRITE) 00E3H (or 01E3h via CMOS Setup)
D7 D6 D5 D4 D3 D2 D1 D0
FPGEN Reserved SPGEN Reserved DPGEN PG2 PG1 PG0
Table 32: Map and Paging Control Register Bit Assignments
Bit Mnemonic Description
D7 FPGEN FLASH Paging Enable — Enables a 64K page frame from E0000h to
EFFFFh. Used to gain access to the on-board FLASH memory.
FPGEN = 0 FLASH page frame disabled.
FPGEN = 1 FLASH page frame enabled.
Note! This bit is for factory use only. It is used to write user default CMOS setup
values to FLASH and to upgrade the system BIOS. When FPGEN = 1, the Page Select
bits are used to access various blocks within the FLASH.
D6 — Reserved — This bit has no function.
D5 SPGEN Battery Backed Static RAM Paging Enable — Enables a 64K page frame
from E0000h to EFFFFh. Used to gain access to an optional Dallas
Semiconductor Battery-Backed Static RAM chip plugged into socket U22
(512KB max.)
SPGEN = 0 BBSRAM page frame disabled.
SPGEN = 1 BBSRAM page frame enabled.
Note! When SPGEN = 1, the Page Select bits are used to access various 64K blocks
within the BBSRAM chip.
D4 — Reserved — This bit has no function.
D3 DPGEN DiskOnChip Enable — Enables a 64K page frame from E0000h to EFFFFh.
Used to gain access to the Disk on Chip
DPGEN = 0 DOC page frame disabled.
DPGEN = 1 DOC page frame enabled.
Note! The Page Select bits are not used when accessing the DOC.
D2-D0 PG2-PG0 Page Select — Selects which 64K block of FLASH or BBSRAM will be mapped
into the page frame at E0000h to EFFFFh
Memory Range within
PG2 PG1 PG0 FLASH or BBSRAM
0 0 0 000000h to 00FFFFh
0 0 1 010000h to 01FFFFh
0 1 0 020000h to 02FFFFh
0 1 1 030000h to 03FFFFh
1 0 0 040000h to 04FFFFh
1 0 1 050000h to 05FFFFh
1 1 0 060000h to 06FFFFh
1 1 1 070000h to 07FFFFh
Note For proper operation, only one page enable bit (FPGEN, SPGEN, or DPGEN)
should be set at a time.