System information

Revision Indicator Register
56 – Reference VSBC-6 Reference Manual
Revision Indicator Register
REVIND (READ ONLY) 00E1h (or 01E1h via CMOS Setup)
D7 D6 D5 D4 D3 D2 D1 D0
PC6 PC5 PC4 PC3 PC2 PC1 PC0 REV0
This register is used to indicate the revision level of the VSBC-6 product.
Bit Mnemonic Description
D7-D1 PC6-PC0 Product Code — These bits are hard coded to represent the product type. The
VSBC-6 will always read as 1111111. Other codes are reserved for future products.
PC6 PC5 PC4 PC3 PC2 PC1 PC0 Product Code
1111111 VSBC-6
Note! This bits are read-only.
D0 REV0 Revision Level — These bits are represent the VSBC-6 circuit revision level.
REV0 Revision Level
0 Rev 5
1 Rev 4 see REV bit in SCR.
Note! This bits are read-only.
Watchdog Timer Hold-Off Register
WDHOLD (WRITE ONLY) 00E1h (or 01E1h via CMOS Setup)
D7 D6 D5 D4 D3 D2 D1 D0
01011010
A watchdog timer circuit is included on the VSBC-6 board to reset the CPU if proper software
execution fails or a hardware malfunction occurs. The watchdog timer is enabled/disabled by
writing to bit D0 of SCR
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate
faster than the timer is set to expire (250 ms minimum). Writing a 5Ah to WDHOLD resets the
watchdog timeout period, preventing the CPU from being reset for the next 250 ms.