System information

Memory and I/O Map
52 – Reference VSBC-6 Reference Manual
Memory and I/O Map
M
EMORY
M
AP
The lower 1 MB memory map of the VSBC-6 is arranged as shown in the following table.
CMOS setup is used to choose between DRAM and PC/104 for three sections of memory from
0C0000h to 0EFFFFh.
Various blocks of memory space between A0000h and FFFFFh can be shadowed. CMOS setup
is used to enable or disable this feature.
Table 29: Memory Map
Start
Address
End
Address Comment
F0000h FFFFFh System BIOS
E0000h EFFFFh Flash Page, System BIOS, DOC, BBSRAM, BIOS Ext.
CC000h DFFFFh PC/104
C0000h CBFFFh Video BIOS
A0000h BFFFFh Video RAM
00000h 9FFFFh DRAM